电子工程世界电子工程世界电子工程世界

关键词

搜索

型号

搜索

SI8902EDB-T1

产品描述TRANSISTOR 2 CHANNEL, N-CHANNEL, Si, SMALL SIGNAL, MOSFET, MICRO FOOT, CSP-6, FET General Purpose Small Signal
产品类别分立半导体    晶体管   
文件大小80KB,共5页
制造商Vishay(威世)
官网地址http://www.vishay.com
下载文档 详细参数 全文预览

SI8902EDB-T1概述

TRANSISTOR 2 CHANNEL, N-CHANNEL, Si, SMALL SIGNAL, MOSFET, MICRO FOOT, CSP-6, FET General Purpose Small Signal

SI8902EDB-T1规格参数

参数名称属性值
是否无铅含铅
是否Rohs认证不符合
厂商名称Vishay(威世)
零件包装代码CSP
包装说明GRID ARRAY, R-PBGA-B6
针数6
制造商包装代码MICRO FOOT
Reach Compliance Codeunknown
配置COMMON DRAIN, 2 ELEMENTS WITH BUILT-IN DIODE AND RESISTOR
最大漏源导通电阻0.072 Ω
FET 技术METAL-OXIDE SEMICONDUCTOR
JESD-30 代码R-PBGA-B6
JESD-609代码e0
元件数量2
端子数量6
工作模式ENHANCEMENT MODE
最高工作温度150 °C
封装主体材料PLASTIC/EPOXY
封装形状RECTANGULAR
封装形式GRID ARRAY
峰值回流温度(摄氏度)240
极性/信道类型N-CHANNEL
最大功率耗散 (Abs)1.7 W
认证状态Not Qualified
表面贴装YES
端子面层Tin/Lead (Sn/Pb)
端子形式BALL
端子位置BOTTOM
处于峰值回流温度下的最长时间30
晶体管应用SWITCHING
晶体管元件材料SILICON

SI8902EDB-T1文档预览

Si8902EDB
New Product
Vishay Siliconix
Bi-Directional N-Channel 20-V (D-S) MOSFET
FEATURES
PRODUCT SUMMARY
V
S1S2
(V)
r
S1S2(on)
(W)
0.045 @ V
GS
= 4.5 V
20
0.048 @ V
GS
= 3.7 V
0.057 @ V
GS
= 2.5 V
0.072 @ V
GS
= 1.8 V
I
S1S2
(A)
5.0
4.8
4.4
3.9
D
D
D
D
TrenchFETr Power MOSFET
Ultra-Low r
SS(on)
ESD Protected: 4000 V
New MICRO FOOTr Chipscale Packaging Reduces
Footprint Area, Profile (0.65 mm) and On-Resistance
Per Footprint Area
APPLICATIONS
D
Battery Protection Circuit
- 1-2 Cell Li+/LiP Battery Pack for Portable Devices
S
1
MICRO FOOT
Bump Side View
Backside View
S
2
5 4
S
2
Pin 1 Identifier
G
1
4 kW
8902E
xxx
G
2
6 3
G
1
Device Marking:
8902E = P/N Code
xxx = Date/Lot Traceability Code
Ordering Information: Si8902EDB-T1
G
2
4 kW
S
1
1
2
S
1
N-Channel
S
2
ABSOLUTE MAXIMUM RATINGS (T
A
= 25_C UNLESS OTHERWISE NOTED)
Parameter
Source1—Source2 Voltage
Gate-Source Voltage
Continuous Source1—Source2 Current (T
J
= 150_C)
a
Pulsed Source1—Source2 Current
Maximum Power Dissipation
a
Operating Junction and Storage Temperature Range
Package Reflow Conditions
c
VPR
IR/Convection
T
A
= 25_C
T
A
= 85_C
T
A
= 25_C
T
A
= 85_C
Symbol
V
S1S2
V
GS
I
S1S2
I
SM
P
D
T
J
, T
stg
5 secs
20
Steady State
"12
Unit
V
5.0
3.4
40
1.7
0.8
- 55 to 150
215
220
3.9
2.8
1
0.5
A
W
_C
THERMAL RESISTANCE RATINGS
Parameter
Maximum J
M i
Junction-to-Ambient
a
ti t A bi t
Maximum Junction-to-Foot
b
t
v
5 sec
Steady State
Steady State
Symbol
R
thJA
R
thJF
Typical
60
95
18
Maximum
75
120
22
Unit
_C/W
C/W
Notes
a. Surface Mounted on 1” x 1” FR4 Board.
b. The Foot is defined as the top surface of the package.
c. Refer to IPC/JEDEC (J-STD-020A), no manual or hand soldering.
Document Number: 71862
S-31863—Rev. D, 15-Sep-03
www.vishay.com
1
Si8902EDB
Vishay Siliconix
New Product
SPECIFICATIONS (T
J
= 25_C UNLESS OTHERWISE NOTED)
Parameter
Static
Gate Threshold Voltage
Gate-Body
Gate Body Leakage
V
GS(th)
I
GSS
V
SS
= V
GS
, I
D
= 980
mA
V
SS
= 0 V, V
GS
=
"4.5
V
V
SS
= 0 V, V
GS
=
"12
V
V
SS
= 16 V, V
GS
= 0 V
V
SS
= 16 V, V
GS
= 0 V, T
J
= 85_C
V
SS
= 5 V, V
GS
= 4.5 V
V
GS
= 4.5 V, I
SS
= 1 A
Source1—Source2 On-State
Source1 Source2 On State Resistance
a
V
GS
= 3.7 V, I
SS
= 1 A
r
S1S2(on)
V
GS
= 2.5 V, I
SS
= 1 A
V
GS
= 1.8 V, I
SS
= 1 A
Forward Transconductance
a
g
fs
V
SS
= 10 V, I
SS
= 1 A
5
0.038
0.041
0.048
0.060
20
0.045
0.048
0.057
0.072
S
W
0.45
1.0
"4
"10
1
5
V
mA
mA
mA
A
Symbol
Test Condition
Min
Typ
Max
Unit
Zero Gate Voltage Source Current
On-State Source Current
a
I
S1S2
I
S(on)
Dynamic
b
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
t
d(on)
t
r
t
d(off)
t
f
V
SS
= 10 V, R
L
= 10
W
I
SS
^
1 A, V
GEN
= 4.5 V, R
G
= 6
W
1
3
17
10
1.5
4.5
26
15
ms
Notes
a. Pulse test; pulse width
v
300
ms,
duty cycle
v
2%.
b. Guaranteed by design, not subject to production testing.
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
20
Gate-Current vs. Gate-Source Voltage
10,000
I
GSS
@ 25_C (mA)
1,000
I
GSS
- Gate Current (
mA)
100
Gate Current vs. Gate-Source Voltage
I
GSS
- Gate Current (mA)
16
12
T
J
= 150_C
10
8
1
0.1
T
J
= 25_C
4
0
0
3
6
9
12
15
V
GS
- Gate-to-Source Voltage (V)
www.vishay.com
0.01
0
3
6
9
12
15
V
GS
- Gate-to-Source Voltage (V)
Document Number: 71862
S-31863—Rev. D, 15-Sep-03
2
Si8902EDB
New Product
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
10
Vishay Siliconix
Output Characteristics
10
Transfer Characteristics
8
I
D
- Drain Current (A)
V
GS
= 5 thru 1.5 V
I
D
- Drain Current (A)
8
6
6
4
4
T
C
= 125_C
2
25_C
- 55_C
2
1V
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
V
DS
- Drain-to-Source Voltage (V)
V
GS
- Gate-to-Source Voltage (V)
0.10
On-Resistance vs. Drain Current
1.6
On-Resistance vs. Junction Temperature
V
GS
= 4.5 V
I
S1S2
= 1 A
r
DS(on)
- On-Resistance (
W
)
V
GS
= 1.8 V
0.06
V
GS
= 2.5 V
r
DS(on)
- On-Resistance (
W)
(Normalized)
10
0.08
1.4
1.2
0.04
V
GS
= 3.7 V
0.02
V
GS
= 4.5 V
1.0
0.8
0.00
0
2
4
6
8
0.6
- 50
- 25
0
25
50
75
100
125
150
I
D
- Drain Current (A)
T
J
- Junction Temperature (_C)
0.10
On-Resistance vs. Gate-to-Source Voltage
I
S1S2
= 5 A
0.2
0.1
Threshold Voltage
r
DS(on)
- On-Resistance (
W
)
0.08
V
GS(th)
Variance (V)
I
S1S2
= 1 A
0.06
I
S1S2
= 980
mA
- 0.0
- 0.1
- 0.2
- 0.3
- 0.4
- 50
0.04
0.02
0.00
0
1
2
3
4
5
V
GS
- Gate-to-Source Voltage (V)
Document Number: 71862
S-31863—Rev. D, 15-Sep-03
- 25
0
25
50
75
100
125
150
T
J
- Temperature (_C)
www.vishay.com
3
Si8902EDB
Vishay Siliconix
New Product
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
Single Pulse Power, Junction-to-Ambient
30
25
20
Power (W)
15
10
10
Limited
by r
DS(on)
Safe Operating Area
0.0001 s
0.001 s
0.01 s
I
D
- Drain Current (A)
1
0.1 s
0.1
T
C
= 25_C
Single Pulse
1s
10 s
dc
5
0
0.01
0.01
0.1
1
Time (sec)
10
100
1000
0.1
1
10
V
DS
- Drain-to-Source Voltage (V)
100
2
1
Normalized Thermal Transient Impedance, Junction-to-Ambient
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
Notes:
0.1
0.1
0.05
0.02
Single Pulse
0.01
10
-4
10
-3
10
-2
10
-1
1
Square Wave Pulse Duration (sec)
P
DM
t
1
t
2
1. Duty Cycle, D =
2. Per Unit Base = R
thJA
= 95_C/W
3. T
JM
- T
A
= P
DM
Z
thJA(t)
4. Surface Mounted
t
1
t
2
10
100
600
2
1
Normalized Thermal Transient Impedance, Junction-to-Foot
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
10
-4
10
-3
10
-2
Square Wave Pulse Duration (sec)
10
-1
1
www.vishay.com
4
Document Number: 71862
S-31863—Rev. D, 15-Sep-03
Si8902EDB
New Product
PACKAGE OUTLINE
MICRO FOOT: 6−BUMP (2 X 3, 0.8−mm PITCH)
6
0.30
X
0.31
Note 3
Solder Mask - 0.4
Vishay Siliconix
Note 2
A
2
e
b Diameter
Bump Note 1
e
e
A
1
A
Recommended Land
8902E
xxx
Mark on Backside of Die
s
e
E
NOTES (Unless Otherwise Specified):
1.
2.
3.
4.
6 solder bumps are Eutetic 63Sn/37Pb with diameter 0.37 - 0.41 mm
Backside surface is coated with a Ag/Ni/Ti layer
Non-solder mask defined copper landing pad.
Laser marks on the silicon die back
e
e
D
s
MILLIMETERS*
Dim
A
A
1
A
2
b
D
E
e
s
INCHES
Min
0.0236
0.102
0.0134
0.0146
0.0598
0.0913
0.0295
0.0150
Min
0.600
0.260
0.340
0.370
1.520
2.320
0.750
0.380
Max
0.650
0.290
0.360
0.410
1.600
2.400
0.850
0.400
Max
0.0256
0.114
0.0142
0.0161
0.0630
0.0945
0.0335
0.0157
* Use millimeters as the primary measurement.
Document Number: 71862
S-31863—Rev. D, 15-Sep-03
www.vishay.com
5

 
EEWorld订阅号

 
EEWorld服务号

 
汽车开发圈

 
机器人开发圈

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版

站点相关: 大学堂 TI培训 Datasheet 电子工程 索引文件: 349  926  772  1361  1396  8  19  16  28  29 

器件索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

北京市海淀区中关村大街18号B座15层1530室 电话:(010)82350740 邮编:100190

电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved