AN2366
Application note
Guidelines for migrating ST72F324 or ST72324 (ROM)
applications to ST72F324B or ST72324B (ROM)
Introduction
This application note provides information on using ST72F324B, ST72324B (ROM)
microcontroller devices in applications originally designed for the ST72F324 and ST72324
(ROM) series.
Table 1.
From
ST72F324,
ST72324
Migration cross-reference table
To
ST72F324B,
ST72324B
Description
8K to 32K program memory, 32-pin and 42-/44-pin
July 2009
Doc ID 12345 Rev 2
1/8
www.st.com
Contents
AN2366
Contents
1
2
ST72F324 migration: feature overview . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Feature compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
2.2
2.3
VDD Rise time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Oscillator pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
4
5
Performance improvements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Limitations summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2/8
Doc ID 12345 Rev 2
AN2366
ST72F324 migration: feature overview
1
ST72F324 migration: feature overview
Table 2.
Feature overview
ST72F324
ST72324 ROM
ST72F324B
ST72324B ROM
Feature
(1)
Package
Program memory
RAM
Operating supply
Register map
I/Os
TQFP44 (10x10) / SDIP42
(2)
/
TQFP32 (7x7) / SDIP32
8K to 32K
384 bytes to 1 Kbyte
3.8V to 5.5V
128 bytes
32/24 Multifunction bidirectional lines
22/17 Alternate function lines
12/10 High sink outputs
Slow / Wait /
Active Halt / Halt
Slow / Wait /
Active Halt / Halt
Yes
Yes
Yes
2 Timers (3/3/2)
(4)
Yes
Yes
Yes
Yes
2 Timers (3/3/2)
Yes
Yes
Yes
No
2 Timers (3/3/2)
Yes
Yes
Yes
(5)
Yes
2 Timers (3/3/2)
Yes
Yes
Yes
(5)
Yes
(6)
Slow / Wait /
Active Halt /
Halt
(3)
Slow / Wait /
Active Halt /
Halt
(3)
Power saving modes
Nested interrupts
MCC / RTC
Watchdog
16-bit timer
(OC / IC / PWM)
SPI
SCI
ADC
LVD
Emulator
Programming tools
ST7MDT20J-EMU3 and ST7MTD20-DVP3 (for Flash devices only)
ST7MDT20J-EPB and ST7MTD20-DVP3 (for Flash devices only)
1. Refer to the corresponding datasheets for more information.
2. SDIP42 / SDIP32 packages are valid only for non-automotive devices.
3. Exit from Active Halt mode available with external interrupts.
4. The TAOC2HR and TAOC2LR registers are write only; reading them will return undefined values and
OCF2 flag in the TACSR register cannot be used (forced to ‘0’ by hardware).
5. Improved ADC accuracy.
6. For 8K and 16K devices, Readout Protection is not supported if LVD is enabled.
Doc ID 12345 Rev 2
3/8
Feature compatibility
AN2366
2
2.1
Feature compatibility
V
DD
Rise time
Some timing differences exist between the products (see
Table 3).
The application must
ensure that the power supply ramps up within the time window specified for the
microcontroller if LVD is ON.
Table 3.
Symbol
V
DD
Rise time
Description
ST72324
ST72324B (8K and 16K)
Device
Conditions
Min
Max
Infinite ms/V
20ms/V
LVD on
ST72324B (32K)
ST72F324, ST72F324B
6µs/V
Infinite ms/V
100ms/V
Vt
POR
V
DD
Rise time
2.2
Asynchronous RESET pin
The V
IL
/V
IH
of RESET pin has been changed from 0.16V
DD
/0.85V
DD
to 0.3V
DD
/0.7V
DD
respectively (see
Table 4).
Table 4.
RESET pin characteristics
ST72F324, ST72324
Min
V
IL
V
IH
-
0.85 x V
DD
Max
0.16 x V
DD
-
ST72F324B, ST72324B
Min
-
0.7 x V
DD
Max
0.3 x V
DD
-
2.3
Oscillator pad
The ST72324B (32K Flash and ROM devices only) features a new oscillator pad which is
more tolerant of the crystal type and is not disturbed if the oscillator pins are left
unconnected. When migrating to these devices, the MCU needs to be validated with your
existing resonator / crystal.
4/8
Doc ID 12345 Rev 2
AN2366
Performance improvements
3
Performance improvements
The ST72F324B devices feature many significant improvements such as:
●
●
●
Reduced PLL clock jitter
Lower power consumption
Improved A/D converter accuracy and negative injection on robust pins
Refer to the relevant datasheets for more details.
Doc ID 12345 Rev 2
5/8