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HYM71V16C735HCT8M-H

产品描述Synchronous DRAM Module, 16MX72, 5.4ns, CMOS, DIMM-168
产品类别存储    存储   
文件大小199KB,共14页
制造商SK Hynix(海力士)
官网地址http://www.hynix.com/eng/
下载文档 详细参数 选型对比 全文预览

HYM71V16C735HCT8M-H概述

Synchronous DRAM Module, 16MX72, 5.4ns, CMOS, DIMM-168

HYM71V16C735HCT8M-H规格参数

参数名称属性值
是否Rohs认证不符合
厂商名称SK Hynix(海力士)
零件包装代码DIMM
包装说明DIMM, DIMM168
针数168
Reach Compliance Codeunknown
ECCN代码EAR99
访问模式FOUR BANK PAGE BURST
最长访问时间5.4 ns
其他特性AUTO/SELF REFRESH
最大时钟频率 (fCLK)133 MHz
I/O 类型COMMON
JESD-30 代码R-XDMA-N168
内存密度1207959552 bit
内存集成电路类型SYNCHRONOUS DRAM MODULE
内存宽度72
功能数量1
端口数量1
端子数量168
字数16777216 words
字数代码16000000
工作模式SYNCHRONOUS
最高工作温度70 °C
最低工作温度
组织16MX72
输出特性3-STATE
封装主体材料UNSPECIFIED
封装代码DIMM
封装等效代码DIMM168
封装形状RECTANGULAR
封装形式MICROELECTRONIC ASSEMBLY
峰值回流温度(摄氏度)NOT SPECIFIED
电源3.3 V
认证状态Not Qualified
刷新周期4096
自我刷新YES
最大待机电流0.11 A
最大压摆率5.5 mA
最大供电电压 (Vsup)3.6 V
最小供电电压 (Vsup)3 V
标称供电电压 (Vsup)3.3 V
表面贴装NO
技术CMOS
温度等级COMMERCIAL
端子形式NO LEAD
端子节距1.27 mm
端子位置DUAL
处于峰值回流温度下的最长时间NOT SPECIFIED

HYM71V16C735HCT8M-H文档预览

16Mx72 bits
PC133 SDRAM Registered DIMM
with PLL, based on 16Mx8 SDRAM with LVTTL, 4 banks & 4K Refresh
HYM71V16C735HCT8M
Series
DESCRIPTION
The Hynix HYM71V16C735HCT8M Series are 16Mx72bits ECC Synchronous DRAM Modules. The modules are composed of nine
16Mx8bits CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package on a 168pin
glass-epoxy printed circuit board. One 0.22uF and one 0.0022uF decoupling capacitors per each SDRAM are mounted on the PCB.
The Hynix HYM71V16C735HCT8M Series are Dual In-line Memory Modules suitable for easy interchange and addition of 128Mbytes
memory. The Hynix HYM71V16C735HCT8M Series are fully synchronous operation referenced to the positive edge of the clock . All
inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high
bandwidth.
FEATURES
PC133/PC100MHz support
168pin SDRAM Registered DIMM
Serial Presence Detect with EEPROM
1.125” (28.56mm) Height PCB with double sided
components
Single 3.3±0.3V power supply
- 1, 2, 4 or 8 or Full page for Sequential Burst
All device pins are compatible with LVTTL interface
- 1, 2, 4 or 8 for Interleave Burst
Data mask function by DQM
Programmable CAS Latency ; 2, 3 Clocks
SDRAM internal banks : four banks
Module bank : one physical bank
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
ORDERING INFORMATION
Part No.
HYM71V16C735HCT8M-K
133MHz
HYM71V16C735HCT8M-H
4 Banks
4K
Normal
TSOP-II
Gold
Clock
Frequency
Internal
Bank
Ref.
Power
SDRAM
Package
Plating
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of
circuits described. No patent licenses are implied.
Rev. 0.1/May.01
PC133 SDRAM Registered DIMM
HYM71V16C735HCT8M Series
PIN DESCRIPTION
PIN
CK0~CK3
CKE0
/S0, /S2
BA0, BA1
A0 ~ A11
/RAS, /CAS, /WE
REGE
DQM0~DQM7
DQ0 ~ DQ63
CB0 ~ CB7
VCC
V
SS
SCL
SDA
SA0~2
WP
NC
PIN NAME
Clock Inputs
Clock Enable
Chip Select
SDRAM Bank Address
Address
Row Address Strobe, Column
Address Strobe, Write Enable
Register Enable
Data Input/Output Mask
Data Input/Output
Check Bit Input/Output
Power Supply (3.3V)
Ground
SPD Clock Input
SPD Data Input/Output
SPD Address Input
Write Protect for SPD
No Connection
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
Enables or disables all inputs except CK, CKE and DQM
Selects bank to be activated during /RAS activity
Selects bank to be read/written during /CAS activity
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA9
Auto-precharge flag : A10
/RAS, /CAS and /WE define the operation
Refer function truth table for details
Register Enable pin which permits the DIMM to operateion in Buffered Mode
when REGE input is Low, in Registered Mode when REGE input is High
Controls output buffers in read mode and masks input data in write mode
Multiplexed data input / output pin
Check bits for ECC
Power supply for internal circuits and input buffers
Ground
Serial Presence Detect Clock input
Serial Presence Detect Data input/output
Serial Presence Detect Address Input
Write Protect for Serial Presence Detect on DIMM
No connection
Rev. 0.1/May.01
3
PC133 SDRAM Registered DIMM
HYM71V16C735HCT8M Series
PIN ASSIGNMENTS
FRONT SIDE
PIN NO.
1
2
3
4
5
6
7
8
9
10
BACK SIDE
PIN NO.
85
86
87
88
89
90
91
92
93
94
FRONT SIDE
PIN NO.
41
42
43
44
45
46
47
48
49
50
51
52
BACK SIDE
PIN NO.
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
NAME
VSS
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
NAME
VSS
DQ32
DQ33
DQ34
DQ35
VCC
DQ36
DQ37
DQ38
DQ39
NAME
VCC
CK0
VSS
NC
/S2
DQM2
DQM3
NC
VCC
NC
NC
CB2
CB3
VSS
DQ16
DQ17
DQ18
DQ19
VCC
DQ20
NC
NC
NC
VSS
DQ21
DQ22
DQ23
VCC
DQ24
DQ25
DQ26
DQ27
VCC
DQ28
DQ29
DQ30
DQ31
VSS
*CK2
NC
WP
SDA
SCL
VCC
NAME
*CK1
NC
VSS
CKE0
NC
DQM6
DQM7
NC
VCC
NC
NC
CB6
CB7
VSS
DQ48
DQ49
DQ50
DQ51
VCC
DQ52
NC
NC
REGE
VSS
DQ53
DQ54
DQ55
VCC
DQ56
DQ57
DQ58
DQ59
VCC
DQ60
DQ61
DQ62
DQ63
VSS
*CK3
NC
SA0
SA1
SA2
VCC
Architecture Key
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VCC
DQ14
DQ15
CB0
CB1
VSS
NC
NC
VCC
/WE
DQM0
DQM1
/S0
NC
VSS
A0
A2
A4
A6
A8
A10/AP
BA1
VCC
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VCC
DQ46
DQ47
CB4
CB5
VSS
NC
NC
VCC
/CAS
DQM4
DQM5
NC
/RAS
VSS
A1
A3
A5
A7
A9
BA0
A11
VCC
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Voltage Key
Note : * CK1 ~ CK3 are connected with termination R/C (Refer to the block diagram)
Rev. 0.1/May.01
4
PC133 SDRAM Registered DIMM
HYM71V16C735HCT8M Series
BLOCK DIAGRAM
Note : 1. The serial resistor values of DQs are 10ohms
2. The padding capacitance of termination R/C for CK1~CK3 is 12pF
Rev. 0.1/May.01
5
PC133 SDRAM Registered DIMM
HYM71V16C735HCT8M Series
SERIAL PRESENCE DETECT
BYTE
NUMBER
BYTE0
BYTE1
BYTE2
BYTE3
BYTE4
BYTE5
BYTE6
BYTE7
BYTE8
BYTE9
BYTE10
BYTE11
BYTE12
BYTE13
BYTE14
BYTE15
BYTE16
BYTE17
BYTE18
BYTE19
BYTE20
BYTE21
BYTE22
BYTE23
BYTE24
BYTE25
BYTE26
BYTE27
BYTE28
BYTE29
BYTE30
BYTE31
BYTE32
BYTE33
BYTE34
BYTE35
BYTE36
~61
BYTE62
BYTE63
BYTE64
BYTE65
~71
FUNCTION
DESCRIPTION
# of Bytes Written into Serial Memory at Module
Manufacturer
Total # of Bytes of SPD Memory Device
Fundamental Memory Type
# of Row Addresses on This Assembly
# of Column Addresses on This Assembly
# of Module Banks on This Assembly
Data Width of This Assembly
Data Width of This Assembly (Continued)
Voltage Interface Standard of This Assembly
SDRAM Cycle Time @/CAS Latency=3
Access Time from Clock @/CAS Latency=3
DIMM Configuration Type
Refresh Rate/Type
Primary SDRAM Width
Error Checking SDRAM Width
Minimum Clock Delay Back to Back Random Column
Address
Burst Lenth Supported
# of Banks on Each SDRAM Device
SDRAM Device Attributes, /CAS Lataency
SDRAM Device Attributes, /CS Lataency
SDRAM Device Attributes, /WE Lataency
SDRAM Module Attributes
SDRAM Device Attributes, General
SDRAM Cycle Time @/CAS Latency=2
Access Time from Clock @/CAS Latency=2
SDRAM Cycle Time @/CAS Latency=1
Access Time from Clock @/CAS Latency=1
Minimum Row Precharge Time (tRP)
Minimum Row Active to Row Active Delay (tRRD)
Minimum /RAS to /CAS Delay (tRCD)
Minimum /RAS Pulse Width (tRAS)
Module Bank Density
Command and Address Signal Input Setup Time
Command and Address Signal Input Hold Time
Data Signal Input Setup Time
Data Signal Input Hold Time
Superset Information (may be used in future)
SPD Revision
Checksum for Byte 0~62
Manufacturer JEDEC ID Code
....Manufacturer JEDEC ID Code
1.5ns
0.8ns
1.5ns
0.8ns
-
Intel SPD 1.2A
-
Hynix JEDED ID
Unused
HSI(Korea Area)
HSA (United States Area)
HSE (Europe Area)
HSJ (Japan Area)
Asia Area
9Fh
ADh
FFh
0*h
1*h
2*h
3*h
4*h
7.5ns
5.4ns
ECC
15.625us
/ Self Refresh Supported
x8
x8
tCCD = 1 CLK
1,2,4,8,Full Page
4 Banks
/CAS Latency=2,3
/CS Latency=0
/WE Latency=0
Registered/Buffered inputs, with PLL
+/- 10% voltage tolerence, Burst Read
Single Bit Write, Precharge All, Auto
Precharge, Early RAS Precharge
7.5ns
5.7ns
-
-
15ns
15ns
15ns
45ns
128MB
1.5ns
0.8ns
1.5ns
0.8ns
15h
08h
15h
08h
00h
12h
3, 8
FUNCTION
-K
128 Bytes
256 Bytes
SDRAM
12
10
1 Bank
72 Bits
-
LVTTL
VALUE
-H
-K
80h
08h
04h
0Ch
0Ah
01h
48h
00h
01h
-H
NOTE
1
7.5ns
5.4ns
75h
54h
02h
80h
08h
08h
01h
8Fh
04h
06h
01h
01h
1Fh
0Eh
75h
54h
00h
00h
0Fh
0Fh
0Fh
2Dh
20h
75h
54h
2
10
6
-
-
20ns
15ns
20ns
45ns
A0h
60h
00h
00h
14h
0Fh
14h
2Dh
15h
08h
15h
08h
E0
BYTE72
Manufacturing Location
10
Rev. 0.1/May.01
6

HYM71V16C735HCT8M-H相似产品对比

HYM71V16C735HCT8M-H HYM71V16C735HCT8M-K
描述 Synchronous DRAM Module, 16MX72, 5.4ns, CMOS, DIMM-168 Synchronous DRAM Module, 16MX72, 5.4ns, CMOS, DIMM-168
厂商名称 SK Hynix(海力士) SK Hynix(海力士)
零件包装代码 DIMM DIMM
包装说明 DIMM, DIMM168 DIMM, DIMM168
针数 168 168
Reach Compliance Code unknown unknown
ECCN代码 EAR99 EAR99
访问模式 FOUR BANK PAGE BURST FOUR BANK PAGE BURST
最长访问时间 5.4 ns 5.4 ns
其他特性 AUTO/SELF REFRESH AUTO/SELF REFRESH
最大时钟频率 (fCLK) 133 MHz 133 MHz
I/O 类型 COMMON COMMON
JESD-30 代码 R-XDMA-N168 R-XDMA-N168
内存密度 1207959552 bit 1207959552 bit
内存集成电路类型 SYNCHRONOUS DRAM MODULE SYNCHRONOUS DRAM MODULE
内存宽度 72 72
功能数量 1 1
端口数量 1 1
端子数量 168 168
字数 16777216 words 16777216 words
字数代码 16000000 16000000
工作模式 SYNCHRONOUS SYNCHRONOUS
最高工作温度 70 °C 70 °C
组织 16MX72 16MX72
输出特性 3-STATE 3-STATE
封装主体材料 UNSPECIFIED UNSPECIFIED
封装代码 DIMM DIMM
封装等效代码 DIMM168 DIMM168
封装形状 RECTANGULAR RECTANGULAR
封装形式 MICROELECTRONIC ASSEMBLY MICROELECTRONIC ASSEMBLY
电源 3.3 V 3.3 V
认证状态 Not Qualified Not Qualified
刷新周期 4096 4096
自我刷新 YES YES
最大待机电流 0.11 A 0.11 A
最大压摆率 5.5 mA 5.5 mA
最大供电电压 (Vsup) 3.6 V 3.6 V
最小供电电压 (Vsup) 3 V 3 V
标称供电电压 (Vsup) 3.3 V 3.3 V
表面贴装 NO NO
技术 CMOS CMOS
温度等级 COMMERCIAL COMMERCIAL
端子形式 NO LEAD NO LEAD
端子节距 1.27 mm 1.27 mm
端子位置 DUAL DUAL
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