Synchronous DRAM Module, 16MX72, 5.4ns, CMOS, DIMM-168
HYM71V16C735HCT8M-K规格参数
参数名称
属性值
厂商名称
SK Hynix(海力士)
零件包装代码
DIMM
包装说明
DIMM, DIMM168
针数
168
Reach Compliance Code
unknown
ECCN代码
EAR99
访问模式
FOUR BANK PAGE BURST
最长访问时间
5.4 ns
其他特性
AUTO/SELF REFRESH
最大时钟频率 (fCLK)
133 MHz
I/O 类型
COMMON
JESD-30 代码
R-XDMA-N168
内存密度
1207959552 bit
内存集成电路类型
SYNCHRONOUS DRAM MODULE
内存宽度
72
功能数量
1
端口数量
1
端子数量
168
字数
16777216 words
字数代码
16000000
工作模式
SYNCHRONOUS
最高工作温度
70 °C
最低工作温度
组织
16MX72
输出特性
3-STATE
封装主体材料
UNSPECIFIED
封装代码
DIMM
封装等效代码
DIMM168
封装形状
RECTANGULAR
封装形式
MICROELECTRONIC ASSEMBLY
电源
3.3 V
认证状态
Not Qualified
刷新周期
4096
自我刷新
YES
最大待机电流
0.11 A
最大压摆率
5.5 mA
最大供电电压 (Vsup)
3.6 V
最小供电电压 (Vsup)
3 V
标称供电电压 (Vsup)
3.3 V
表面贴装
NO
技术
CMOS
温度等级
COMMERCIAL
端子形式
NO LEAD
端子节距
1.27 mm
端子位置
DUAL
HYM71V16C735HCT8M-K文档预览
16Mx72 bits
PC133 SDRAM Registered DIMM
with PLL, based on 16Mx8 SDRAM with LVTTL, 4 banks & 4K Refresh
HYM71V16C735HCT8M
Series
DESCRIPTION
The Hynix HYM71V16C735HCT8M Series are 16Mx72bits ECC Synchronous DRAM Modules. The modules are composed of nine
16Mx8bits CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package on a 168pin
glass-epoxy printed circuit board. One 0.22uF and one 0.0022uF decoupling capacitors per each SDRAM are mounted on the PCB.
The Hynix HYM71V16C735HCT8M Series are Dual In-line Memory Modules suitable for easy interchange and addition of 128Mbytes
memory. The Hynix HYM71V16C735HCT8M Series are fully synchronous operation referenced to the positive edge of the clock . All
inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high
bandwidth.
FEATURES
•
•
•
•
PC133/PC100MHz support
168pin SDRAM Registered DIMM
Serial Presence Detect with EEPROM
1.125” (28.56mm) Height PCB with double sided
components
Single 3.3±0.3V power supply
- 1, 2, 4 or 8 or Full page for Sequential Burst
•
•
All device pins are compatible with LVTTL interface
- 1, 2, 4 or 8 for Interleave Burst
Data mask function by DQM
•
Programmable CAS Latency ; 2, 3 Clocks
•
•
•
•
•
•
SDRAM internal banks : four banks
Module bank : one physical bank
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
ORDERING INFORMATION
Part No.
HYM71V16C735HCT8M-K
133MHz
HYM71V16C735HCT8M-H
4 Banks
4K
Normal
TSOP-II
Gold
Clock
Frequency
Internal
Bank
Ref.
Power
SDRAM
Package
Plating
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of
circuits described. No patent licenses are implied.
Rev. 0.1/May.01
PC133 SDRAM Registered DIMM
HYM71V16C735HCT8M Series
PIN DESCRIPTION
PIN
CK0~CK3
CKE0
/S0, /S2
BA0, BA1
A0 ~ A11
/RAS, /CAS, /WE
REGE
DQM0~DQM7
DQ0 ~ DQ63
CB0 ~ CB7
VCC
V
SS
SCL
SDA
SA0~2
WP
NC
PIN NAME
Clock Inputs
Clock Enable
Chip Select
SDRAM Bank Address
Address
Row Address Strobe, Column
Address Strobe, Write Enable
Register Enable
Data Input/Output Mask
Data Input/Output
Check Bit Input/Output
Power Supply (3.3V)
Ground
SPD Clock Input
SPD Data Input/Output
SPD Address Input
Write Protect for SPD
No Connection
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
Enables or disables all inputs except CK, CKE and DQM
Selects bank to be activated during /RAS activity
Selects bank to be read/written during /CAS activity
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