FINAL
Am28F010A
1 Megabit (128 K x 8-Bit)
CMOS 12.0 Volt, Bulk Erase Flash Memory with Embedded Algorithms
DISTINCTIVE CHARACTERISTICS
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High performance
— Access times as fast as 70 ns
s
CMOS low power consumption
— 30 mA maximum active current
— 100 µA maximum standby current
— No data retention power consumption
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Compatible with JEDEC-standard byte-wide
32-pin EPROM pinouts
— 32-pin PDIP
— 32-pin PLCC
— 32-pin TSOP
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100,000 write/erase cycles minimum
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Write and erase voltage 12.0 V
±5%
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Latch-up protected to 100 mA from
–1 V to V
CC
+1 V
s
Embedded Erase Electrical Bulk Chip Erase
— 5 seconds typical chip erase, including
pre-programming
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Embedded Program
— 14 µs typical byte program, including time-out
— 4 seconds typical chip program
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Command register architecture for
microprocessor/microcontroller compatible
write interface
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On-chip address and data latches
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Advanced CMOS flash memory technology
— Low cost single transistor memory cell
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Embedded algorithms for completely self-timed
write/erase operations
GENERAL DESCRIPTION
The Am28F010A is a 1 Megabit Flash memory orga-
nized as 128 Kbytes of 8 bits each. AMD’s Flash memo-
ries offer the most cost-effective and reliable read/write
non-volatile random access memory. The Am28F010A
is packaged in 32-pin PDIP, PLCC, and TSOP versions.
It is designed to be reprogrammed and erased in-system
or in standard EPROM programmers. The Am28F010A
is erased when shipped from the factory.
The standard Am28F010A offers access times of as fast
as 70 ns, allowing high speed microprocessors to
operate without wait states. To eliminate bus contention,
the device has separate chip enable (CE#) and output
enable (OE#) controls.
AMD’s Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
Am28F010A uses a command register to manage this
functionality. The command register allows for 100%
TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining
maximum EPROM compatibility.
T h e A m 28 F 0 10 A i s com p a tibl e w i th th e A M D
Am28F256A, Am28F512A, and Am28F020A Flash
memories. All devices in the Am28Fxxx family follow the
JEDEC 32-pin pinout standard. In addition, all devices
Publication#
16778
Rev:
D
Amendment/+2
Issue Date:
May 1998
within this family that offer Embedded Algorithms use
the same command set. This offers designers the flexi-
bility to retain the same device footprint and command
set, at any density between 256 Kbits and 2 Mbits.
AMD’s Flash technology reliably stores memory con-
tents even after 100,000 erase and program cycles. The
AMD cell is designed to optimize the erase and program-
ming mechanisms. In addition, the combination of
advanced tunnel oxide processing and low internal elec-
tric fields for erase and programming operations pro-
duces reliable cycling. The Am28F010A uses a
12.0±5% V
PP
input to perform the erase and program-
ming functions.
The highest degree of latch-up protection is achieved
with AMD’s proprietary non-epi process. Latch-up pro-
tection is provided for stresses up to 100 mA on address
and data pins from –1 V to V
CC
+1 V.
AMD’s Flash technology combines years of EPROM and
EEPROM experience to produce the highest levels of
quality, reliability, and cost effectiveness. The
Am28F010A electrically erases all bits simultaneously
using Fowler-Nordheim tunneling. The bytes are
programmed one byte at a time using the EPROM pro-
gramming mechanism of hot electron injection.
Embedded Program
The Am28F010A is byte programmable using the
Embedded Program algorithm, which does not require
the system to time-out or verify the data programmed.
The typical room temperature programming time of this
device is two seconds.
Embedded Erase
The entire device is bulk erased using the Embedded
Erase algorithm, which automatically programs the
entire array prior to electrical erase. The timing and ver-
ification of electrical erase are controlled internal to the
device. Typical erasure time at room temperature is five
seconds, including preprogramming.
Comparing Embedded Algorithms with Flasherase and Flashrite Algorithms
Am28F010A with
Embedded Algorithms
Embedded
Programming
Algorithm vs.
Flashrite
Programming
Algorithm
AMD’s Embedded Programming algorithm
requires the user to only write a program
set-up command and a program command
(program data and address). The device
automatically times the programming
pulse width, verifies the programming, and
counts the number of sequences. A status
bit, Data
#
Polling, provides the user with
the programming operation status.
Am28F010 using AMD Flashrite
and Flasherase Algorithms
The Flashrite Programming algorithm requires the
user to write a program set-up command, a program
command, (program data and address), and a
program verify command, followed by a read and
compare operation. The user is required to time the
programming pulse width in order to issue the
program verify command. An integrated stop timer
prevents any possibility of overprogramming.
Upon completion of this sequence, the data is read
back from the device and compared by the user with
the data intended to be written; if there is not a
match, the sequence is repeated until there is a
match or the sequence has been repeated 25 times.
The Flasherase Erase algorithm requires the device
to be completely programmed prior to executing an
erase command.
To invoke the erase operation, the user writes an
erase set-up command, an erase command, and an
erase verify command. The user is required to time
the erase pulse width in order to issue the erase
verify command. An integrated stop timer prevents
any possibility of overerasure.
Upon completion of this sequence, the data is read
back from the device and compared by the user with
erased data. If there is not a match, the sequence is
repeated until there is a match or the sequence has
been repeated 1,000 times.
Embedded Erase
Algorithm vs.
Flasherase Erase
Algorithm
AMD’s Embedded Erase algorithm
requires the user to only write an erase set-
up command and erase command. The
device automatically pre-programs and
verifies the entire array. The device then
automatically times the erase pulse width,
verifies the erase operation, and counts
the number of sequences. A status bit,
Data
#
Polling, provides the user with the
erase operation status.
Commands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine,
which controls the erase and programming circuitry.
During write cycles, the command register internally
latches addresses and data needed for the program-
ming and erase operations. For system design simpli-
fication, the Am28F010A is designed to support either
WE# or CE# controlled writes. During a system write
cycle, addresses are latched on the falling edge of
WE# or CE#, whichever occurs last. Data is latched
on the rising edge of WE# or CE#, whichever occurs
first. To simplify the following discussion, the WE# pin
is used as the write cycle control pin throughout the
rest of this text. All setup and hold times are with
respect to the WE# signal.
2
Am28F010A
FPGA/CPLD
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