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NSS60101DMT

产品描述60 V, 1 A, Low VCE(sat) NPN Transistors
文件大小90KB,共6页
制造商ON Semiconductor(安森美)
官网地址http://www.onsemi.cn
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NSS60101DMT概述

60 V, 1 A, Low VCE(sat) NPN Transistors

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NSS60101DMT
60 V, 1 A, Low V
CE(sat)
NPN
Transistors
ON Semiconductor’s e
2
PowerEdge family of low V
CE(sat)
transistors are miniature surface mount devices featuring ultra low
saturation voltage (V
CE(sat)
) and high current gain capability. These
are designed for use in low voltage, high speed switching applications
where affordable efficient energy control is important.
Typical applications are DC−DC converters and LED lightning,
power management…etc. In the automotive industry they can be used
in air bag deployment and in the instrument cluster. The high current
gain allows e
2
PowerEdge devices to be driven directly from PMU’s
control outputs, and the Linear Gain (Beta) makes them ideal
components in analog amplifiers.
Features
www.onsemi.com
60 Volt, 1 Amp
NPN Low V
CE(sat)
Transistors
MARKING
DIAGRAM
WDFN6
CASE 506AN
1
1
2 AN MG
G
3
6
5
4
NSV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable
NSV60101DMTWTBG − Wettable Flanks Device
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
MAXIMUM RATINGS
(T
A
= 25°C)
Rating
Collector−Emitter Voltage
Collector−Base Voltage
Emitter−Base Voltage
Collector Current − Continuous
Collector Current − Peak
Symbol
V
CEO
V
CBO
V
EBO
I
C
I
CM
Max
60
60
6
1
2
Unit
Vdc
Vdc
Vdc
A
A
AN = Specific Device Code
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
6
5
4
8
1
2
3
7
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
6,7
1
THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance Junction−to−Ambient
(Notes 1 and 2)
Total Power Dissipation per Package @
T
A
= 25°C (Note 2)
Thermal Resistance Junction−to−Ambient
(Note 3)
Power Dissipation per Transistor @ T
A
= 25°C
(Note 3)
Junction and Storage Temperature Range
Symbol
R
qJA
P
D
R
qJA
P
D
T
J
, T
stg
Max
55
2.27
69
1.8
−55 to
+150
Unit
°C/W
5
2
4
W
°C/W
W
°C
3,8
ORDERING INFORMATION
Device
NSS60101DMTTBG
NSV60101DMTWTBG
Package
WDFN6
(Pb−Free)
WDFN6
(Pb−Free)
Shipping
3000/Tape &
Reel
3000/Tape &
Reel
1. Per JESD51−7 with 100 mm
2
pad area and 2 oz. Cu (Dual Operation).
2. P
D
per Transistor when both are turned on is one half of Total P
D
or 1.13 Watts.
3. Per JESD51−7 with 100 mm
2
pad area and 2 oz. Cu (Single−Operation).
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2016
1
July, 2016 − Rev. 2
Publication Order Number:
NSS60101DMT/D

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描述 60 V, 1 A, Low VCE(sat) NPN Transistors 60 V, 1 A, Low VCE(sat) NPN Transistors 60 V, 1 A, Low VCE(sat) NPN Transistors
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