CMX910
AIS Baseband Processor
D/910/6 March 2009
Provisional Issue
Features:
•
Half-Duplex GM(F)SK, FSK and DSC Capabilities
•
Slot/Sample Counter with UTC Timing Interface
•
Optimum Co-channel and Adjacent-channel
Performance
•
Flexible Signal Channels
– Two Simultaneous Rx
– One Tx
– Optional FSK Interface
•
AIS Data Formatted and Raw Data Modes
•
Supports Carrier-Sensing Channel Access
(CSTDMA) Operation
•
RF Device-Enable Facilities
•
C-BUS Serial Interface with Expansion Port
•
I and Q Radio Interface
•
Low-Power (3.0 to 3.6V) Operation
•
Low Profile, 64-lead LQFP (L9) and
Leadless VQFN (Q1) Packages
•
Auxiliary ADC and DAC Functions
– 5 x (10-bit) DACs
– 5-Input MUX (10-bit) ADC
Applications:
•
Automatic Identification System
(AIS) for Marine Safety
•
Class A or B AIS Transponders
•
AIS Rx-only Modules
Aux
ADC
Aux
DACs
CMX910
Radio
Rx1: I/Q
down-
converter
RF
Tx: I/Q
up-
converter
Rx2: I/Q
down-
converter
Optional
FSK
Demod.
(FX604)
Σ−Δ
ADCs
GMSK/
FSK
decoder
GMSK/
FSK
encoder
GMSK/
FSK
decoder
HDLC/
NRZI
decoder
Message
buffer
HDLC/
NRZI
decoder
Message
buffers
HDLC/
NRZI
encoder
Message
buffers
C-BUS
Expansion
Port
C-BUS
Interface
Host µC
Σ−Δ
DACs
Σ−Δ
ADCs
Other
C-BUS
Devices
Device
Enable
Port
FSK
Retiming
(External)
Reset and
Power
Control
Slot and
Sample
Timer
Interrupt
Generator
GNSS
Engine
TCXO
1.
Brief Description
A highly integrated Baseband Signalling Processor IC, the CMX910 fulfils the requirements of the class A
and class B marine Automatic Identification System (AIS) transponder market. The CMX910 is half duplex
in operation, comprising two parallel I+Q Rx paths and one Tx path. These are configurable for AIS or
DSC operation. The device performs channel filtering and signal modulation/demodulation with
associated AIS functions, such as training sequence detection, NRZI conversion and HDLC processing
(flags, bit stuffing/de-stuffing, CRC generate/check). An external 1200bps FSK demodulator interface
provides a third parallel decode path for DSC, as required by the class A market. Integrated Rx/Tx data
buffers and a flexible slot/sample timer are also provided, all of which greatly reduce the processing
requirements of the host µC. Provision of a C-BUS expansion port, an RF device enable port and a
number of auxiliary ADCs and DACs further simplifies the system hardware design, reducing the overall
equipment cost and size.
©
2009 CML Microsystems Plc
AIS Baseband Processor
CMX910
CONTENTS
Section
1.
2.
3.
4.
5.
Page
Brief Description .................................................................................................1
Block Diagram .....................................................................................................4
Signal List ............................................................................................................5
External Components .........................................................................................7
General Description ............................................................................................8
5.1
Overview of CMX910 Operation............................................................8
5.2
C-BUS Interface......................................................................................9
Reset and Power Control ....................................................................12
5.3
5.3.1 RESETN pin .............................................................................12
5.3.2 General Reset Command .......................................................12
5.3.3 Clock Control...........................................................................12
Slot and Sample Timer ........................................................................13
5.4
5.4.1 Manual Nudge..........................................................................16
5.4.2 Auto Nudge..............................................................................17
5.4.3 Sleep Mode ..............................................................................17
5.4.4 Selecting the Nudge_Trigger Value ......................................18
5.5
Transmit Operation ..............................................................................19
5.5.1 Transmitter Registers.............................................................19
5.5.2 AIS Raw Mode Transmit .........................................................24
5.5.3 AIS Burst Mode Transmit .......................................................25
5.5.4 DSC Transmit ..........................................................................27
5.5.5 Transmitter Timing Control....................................................29
5.6
Receive Operation................................................................................32
5.6.1 Receiver Registers..................................................................33
5.6.2 AIS Raw Mode Receive...........................................................37
5.6.3 AIS Burst Mode Receive.........................................................38
5.6.4 DSC Receive (Main Channel) .................................................39
5.6.5 DSC Receive (External FSK Interface)..................................39
5.7
Auxiliary A-to-D Converter ..................................................................40
5.8
Auxiliary D-to-A Converters................................................................42
5.9
Interrupt Generator ..............................................................................46
5.10
Device Enable Port...............................................................................48
5.11
C-BUS Expansion Port ........................................................................49
5.12
Special Command Interface................................................................50
Supplementary Information .............................................................................52
6.1
Glossary of Terms................................................................................52
Performance Specification...............................................................................54
7.1
Electrical Performance ........................................................................54
7.1.1 Absolute Maximum Ratings...................................................54
7.1.2 Operating Limits......................................................................54
7.1.3 Operating Characteristics ......................................................55
7.2
Packaging .............................................................................................60
6.
7.
©
2009 CML Microsystems Plc
2
D/910/6
AIS Baseband Processor
CMX910
Page
Table
Table 1 Summary of C-BUS Registers ............................................................................ 11
Table 2 Example Tx Event Sequence Setup ................................................................... 31
Figure
Page
Figure 1 CMX910 Block Diagram ...................................................................................... 4
Figure 2 Recommended External Components................................................................. 7
Figure 3 Basic C-BUS Transactions .................................................................................. 9
Figure 4 C-BUS Data-Streaming Operation .................................................................... 10
Figure 5 Slot and Sample Timer Circuit ........................................................................... 13
Figure 6 Transmit Channel .............................................................................................. 19
Figure 7 Tx (AIS raw mode) state transitions .................................................................. 25
Figure 8 Tx (AIS burst mode) state transitions ................................................................ 27
Figure 9 Tx (DSC mode) state transitions........................................................................ 28
Figure 10 Typical AIS Transmission ................................................................................ 29
Figure 11 Receive Channel ............................................................................................. 32
Figure 12 Auxiliary ADC................................................................................................... 40
Figure 13 Auxiliary DACs ................................................................................................. 42
Figure 14 RAMDAC Values ............................................................................................. 45
Figure 15 I/Q Filter response in 25kHz operation. ........................................................... 59
Figure 16 C-BUS Timing .................................................................................................. 59
Figure 17 Q1 Mechanical Outline:
Order as part no. CMX910Q1
.................................. 60
Figure 18 L9 Mechanical Outline:
Order as part no. CMX910L9....................................
61
History
Version
1-5
6
Changes
Earlier versions, for which a history file is not maintained.
•
Corrected description of the operation of the Auto Nudge Acquire sequence in
section 5.4.2.
Date
20/11/0
8
26/03/0
9
It is always recommended that you check for the latest product datasheet version from the
Datasheets page of the CML website: [www.cmlmicro.com].
©
2009 CML Microsystems Plc
3
D/910/6
AIS Baseband Processor
CMX910
2.
Block Diagram
AUXADC2FB
AUXADC2N
AUXADC2P
AUXADC1FB
AUXADC1N
AUXADC1P
AUXADC0FB
AUXADC0N
AUXADC0P
AUXADC3
AUXADC4
AUXDAC4
AUXDAC3
AUXDAC2
AVDD
AVSS
10-bit
ADC
AUXDAC1
AUXDAC0
10-bit
DAC
10-bit
DAC
10-bit
DAC
10-bit
DAC
10-bit
DAC
MUX
S/H
DAC
RAM
Aux ADC
Aux DACs
Digital
2V5
regulator
AVSS
IRX1P
IRX1N
QRX1P
QRX1N
VBIAS
ITXP
ITXN
QTXP
QTXN
AVSS
BIAS
gen.
Σ−Δ
DAC
Σ−Δ
DAC
Σ−Δ
ADC
Σ−Δ
ADC
IOVDD
DVDD
I
Q
dφ
dt
Level Tracking
GMSK
Slicer
FSK
demod.
HDLC/
NRZI
decoder
Message
buffers
Rx1
FIFO
Special
Command
Interface
Rx Channel 1
I
Q
cos
dt
FSK
mod.
Message
buffer
HDLC/
NRZI
encoder
Tx
FIFO
sin
RDATA
SCLK
CDATA
CSN
CSXN
DVSS
EXP5N
EXP4N
EXP3N
EXP2N
EXP1N
EXP0N
C-BUS
Interface
Tx Channel
C-BUS
Expansion Port
IRX2P
IRX2N
QRX2P
QRX2N
Σ−Δ
ADC
Σ−Δ
ADC
I
Q
dφ
dt
Level Tracking
GMSK
Slicer
FSK
demod.
HDLC/
NRZI
decoder
Message
buffers
Rx2
FIFO
Rx Channel 2
AVDD
Analogue
2V5
regulator
Device Enable Port
FSK
retiming
FSK
FIFO
FSK Rx (Ext.)
Reset and
Power
Control
Slot and
Sample
Timer
Interrupt
Generator
©
2009 CML Microsystems Plc
IOVDD
ENAB5
ENAB4
ENAB3
ENAB2
ENAB1
ENAB0
Figure 1 CMX910 Block Diagram
DVSS
FSK_RXD
FSK_DET
FSK_MUTE
REFCLK
RESETN
UTC1PPS
SLOTCLKN
IRQN
4
D/910/6
AIS Baseband Processor
CMX910
3.
Signal List
Signal
Description
Package
Q1 or L9
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Name
AV
SS
IRX1P
IRX1N
Type
Power
I/P
I/P
I/P
I/P
O/P
O/P
O/P
O/P
O/P
Power
I/P
I/P
I/P
I/P
Power
Power
O/P
O/P
O/P
O/P
O/P
O/P
Power
I/P
I/P
I/P
I/P
I/P
I/P
O/P
Analogue negative supply rail (ground)
Receive “I” channel 1, positive input
Receive “I” channel 1, negative input
Receive “Q” channel 1, positive input
Receive “Q” channel 1, negative input
A bias line for the internal circuitry, held at ½ AV
DD
. This pin must
be decoupled to AV
SS
by a capacitor mounted close to the device
pins
Transmit “I” channel, positive output
Transmit “I” channel, negative output
Transmit “Q” channel, positive output
Transmit “Q” channel, negative output
Analogue negative supply rail (ground)
Receive “I” channel 2, positive input
Receive “I” channel 2, negative input
Receive “Q” channel 2, positive input
Receive “Q” channel 2, negative input
Analogue positive supply rail. Decouple to AV
SS
Digital I/O positive supply rail. Decouple to DV
SS
Enable output 0
Enable output 1
Enable output 2
Enable output 3
Enable output 4
Enable output 5
Digital negative supply rail (ground)
FSK RF squelch indicator
FSK baseband energy detect indicator
Raw FSK demodulator input data
Master input clock (multiple of 2.4MHz)
Active low chip reset
1Hz UTC sync pulse, typically from GNSS receiver
Slot clock output (active low), pulses at the start of each AIS slot.
Configurable as a ‘wire-ORable’ output, requiring an external pullup
resistor, or as an active pullup/pulldown.
A ‘wire-ORable’ output for connection to the host µC's Interrupt
Request input. This output has a low impedance pull down to DVSS
when active and is high impedance when inactive. An external
pullup resistor is required.
QRX1P
QRX1N
VBIAS
ITXP
ITXN
QTXP
QTXN
AV
SS
IRX2P
IRX2N
QRX2P
QRX2N
AV
DD
IOV
DD
ENAB0
ENAB1
ENAB2
ENAB3
ENAB4
ENAB5
DV
SS
FSK_MUTE
FSK_DET
FSK_RXD
REFCLK
RESETN
UTC1PPS
SLOTCLKN
32
IRQN
O/P
©
2009 CML Microsystems Plc
5
D/910/6
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