CMX7261
CML Microcircuits
COMMUNICA
TION SEMICONDUCTORS
Multi-transcoder
D/7261_FI-1.x/9 March 2012
DATASHEET
7261 FI-1.x Multi-transcoder
Advance Information
Features
Half-duplex operation
Full-duplex operation
Multiple codec support:
o
PCM (linear, µ-law, A-law), CVSD and
G.729A codecs
Multiple transcoding support:
o
PCM to CVSD and reverse
o
PCM to G.729A and reverse
o
CVSD to G.729A and reverse
o
PCM μ/A/linear to PCM μ/A/linear
transcoder
No external DSP or codecs required: simply
upload Function Image™ (FI)
Transcoder routing:
o
Choice of input sources – C-BUS transfer
to host, external PCM device/codec,
analogue audio input
o
Choice of output sources – C-BUS transfer
to host, external PCM device/codec,
analogue audio output
Voice activity detection
C-BUS host serial interface
o
SPI-like with register addressing
o
Read/Write 128-byte FIFOs and data buffers
to streamline transfers and relax host service
latency
Auxiliary functions
o
Three GPIOs
o
Analogue input/output gain adjustment
o
Analogue input multiplexer
o
Analogue output multiplexer
Master/Slave PCM serial interface
o
For external audio CODEC
Low power 3.3V operation with powersave
functions
Small 64-pin VQFN/LQFP package
Applications
Half duplex digital radio systems
Full duplex digital radio systems
Personal area network voice links
Privacy-type digital voice communications
Wireless PBX
VoIP applications
Digital Software Defined Radio (SDR)
GPIOs
Registers
Analogue In
ADC
Digital
Filters
Digital
Filters
FIFO
Configuration
Transcoder
Function
Image™
Analogue Out
DAC
PCM Talk-
Through /
PCM
C-BUS
Host
µC
Transcoder
External ADC /
DAC
This document contains:
3.3V
3.3V
CMX7261
Multi-transcoder
Datasheet
User
Manual
2012 CML Microsystems Plc
CMX7261 Voice Multi-transcoder
CMX7261
1
Brief Description
The CMX7261 Multi-transcoder IC is a device supporting multiple speech codecs in a single chip. The
CMX7261 is capable of encoding analogue voice into PCM (linear, µ-law or A-law), CVSD or G.729A data
formats. It is capable of decoding PCM, CVSD and G.729A back to analogue voice. It can also transcode
data between PCM, CVSD and G.729A.
Input and output signals may be passed through the C-BUS interface, the PCM port or the on-chip
convertors (ADC/DAC).
The device utilises CML’s proprietary
FirmASIC
component technology. On-chip sub-systems are
configured by a Function Image™ data file that is uploaded during device initialisation and defines the
device's function and feature set. The Function Image™ can be loaded automatically from a host µC over
the C-BUS serial interface or from an external memory device. The device's functions and features can be
enhanced by subsequent Function Image™ releases, facilitating in-the-field upgrades.
The CMX7261 operates from a 3.3V supply and includes selectable powersaving modes. It is available in
a 64-VQFN (Q1) or a 64-LQFP (L9) package.
Note that text shown in pale grey indicates features that will be supported in future versions of the device.
This Data Sheet is the first part of a two-part document.
2012 CML Microsystems Plc
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D/7261_FI-1.x/9
CMX7261 Voice Multi-transcoder
CMX7261
CONTENTS
Section
1
2
Page
Brief Description ...................................................................................................................... 2
1.1
History........................................................................................................................... 5
Block Diagrams........................................................................................................................ 7
2.1
Half Duplex Transcoder ................................................................................................ 7
2.2
Full Duplex Transcoder ................................................................................................ 8
Pin and Signal List................................................................................................................... 9
3.1
Signal Definitions ........................................................................................................ 12
PCB Layout Guidelines and Power Supply Decoupling .................................................... 13
External Components............................................................................................................ 14
5.1
Xtal Interface............................................................................................................... 14
5.2
C-BUS Interface.......................................................................................................... 14
5.3
PCM and Serial Port Interface .................................................................................... 15
5.4
Audio Output ............................................................................................................... 16
5.4.1 Audio Output Routing ........................................................................................... 16
5.4.2 Audio Output Reconstruction Filter ...................................................................... 17
5.5
Audio Input .................................................................................................................. 19
5.5.1 Audio Input Routing .............................................................................................. 19
5.5.2 Differential Audio Input ......................................................................................... 19
5.5.3 Single-Ended Audio Input Interface ..................................................................... 19
5.6
GPIO Pins ................................................................................................................... 20
General Description............................................................................................................... 21
6.1
CMX7261 Features..................................................................................................... 21
6.2
Signal Interfaces ......................................................................................................... 22
Detailed Descriptions ............................................................................................................ 23
7.1
Xtal Frequency............................................................................................................ 23
7.2
Host Interface ............................................................................................................. 23
7.2.1 C-BUS Operation ................................................................................................. 23
7.3
Function Image™ Loading.......................................................................................... 26
7.3.1 FI Loading from Host Controller ........................................................................... 26
7.3.2 FI Loading from Serial Memory ............................................................................ 28
7.4
Coding Formats .......................................................................................................... 29
7.4.1 G.711 ................................................................................................................... 29
7.4.2 G.729A ................................................................................................................. 29
7.4.3 CVSD ................................................................................................................... 30
7.5
Transcoding Description ............................................................................................. 32
7.5.1 Input and Output Frame Sizes ............................................................................. 32
7.5.2 Data Transfer Using C-BUS Interface.................................................................. 32
7.5.3 Data Formats – Packed and Unpacked ............................................................... 37
7.5.4 Data Formats – 8kHz, 16kHz or 32kHz Sample Rate.......................................... 40
7.6
Voice Activity Detection .............................................................................................. 41
7.6.1 Attack and Decay Time Constant Programming .................................................. 43
7.6.2 Threshold Level Programming ............................................................................. 43
7.6.3 Signal to Noise Hangover..................................................................................... 43
3
4
5
6
7
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CMX7261 Voice Multi-transcoder
CMX7261
7.6.4 VAD Output Interface ........................................................................................... 43
7.6.5 VAD Output Level................................................................................................. 44
7.7
Device Control ............................................................................................................ 44
7.7.1 Normal Operation Overview ................................................................................. 45
7.7.2 Transcoder Operation .......................................................................................... 45
7.7.3 Device Configuration (Using the Programming Register) .................................... 51
7.7.4 Device Configuration (Using dedicated registers) ................................................ 51
7.7.5 Interrupt Operation ............................................................................................... 51
7.7.6 PCM Port .............................................................................................................. 52
7.8
Signal Level Optimisation ........................................................................................... 52
7.8.1 Audio Output Path Levels..................................................................................... 52
7.8.2 Audio Input Path Levels ....................................................................................... 52
7.9
C-BUS Register Summary.......................................................................................... 53
8
Performance Specification ................................................................................................... 54
8.1
Electrical Performance ............................................................................................... 54
8.1.1 Absolute Maximum Ratings ................................................................................. 54
8.1.2 Operating Limits ................................................................................................... 54
8.1.3 Operating Characteristics..................................................................................... 55
8.1.4 CMX7261: 7261 FI-1.x Parametric Performance ................................................. 58
8.1.5 CVSD Typical Performance ................................................................................. 59
8.2
C-BUS Timing ............................................................................................................. 60
8.3
PCM Port Timing ........................................................................................................ 61
8.3.1 PCM Internal Clock .............................................................................................. 61
8.3.2 PCM External Clock ............................................................................................. 62
8.4
Packaging ................................................................................................................... 63
Page
Input and Output Ports – Full Duplex Mapping .................................................................. 8
Definition of Power Supply and Reference Voltages........................................................ 12
BOOTEN Pin States ......................................................................................................... 26
C-BUS Registers .............................................................................................................. 53
Page
Table
Table 1
Table 2
Table 3
Table 4
Figure
Figure 1 Block Diagram ................................................................................................................... 7
Figure 2 Full Duplex Block Diagram ................................................................................................ 8
Figure 3 CMX7261 Power Supply and De-coupling ...................................................................... 13
Figure 4 Recommended External Components – Xtal Interface................................................... 14
Figure 5 Recommended External Components – C-BUS Interface.............................................. 14
Figure 6 Interfacing the CMX7261 to an External Codec (master) and Serial Memory ................ 15
Figure 7 Interfacing the CMX7261 to an External Codec (slave) and Serial Memory................... 16
Figure 8 Analogue Audio Output Routing...................................................................................... 17
Figure 9 Recommended External Components – ANAOUT/MONOUT Reconstruction Filter...... 18
Figure 10 Recommended External Components – Speaker2 Output........................................... 18
Figure 11 Recommended External Components – Speaker1 Output........................................... 18
Figure 12 Analogue Audio Input Routing ...................................................................................... 19
Figure 13 Recommended External Components – Single-Ended Audio Input Interface .............. 20
Figure 14 CMX7261 Inputs and Outputs ....................................................................................... 22
2012 CML Microsystems Plc
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D/7261_FI-1.x/9
CMX7261 Voice Multi-transcoder
CMX7261
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Figure 35
Basic C-BUS Transactions ........................................................................................... 24
C-BUS Data-Streaming Operation ................................................................................ 25
FI Loading from Host .................................................................................................... 27
FI Loading from Serial Memory..................................................................................... 28
Block Diagram of Conceptual CELP Synthesis Model .................................................. 30
CVSD Encoder .............................................................................................................. 31
CVSD Decoder.............................................................................................................. 31
Audio Input and Audio Output FIFOs ............................................................................ 33
Input Data Transfer into the CMX7261 ......................................................................... 36
Output Data Transfer from the CMX7261 ..................................................................... 37
Examples of Sample Rate Conversion ......................................................................... 41
VAD Block Diagram ...................................................................................................... 42
Transcoder Operation Flowchart .................................................................................. 46
Full duplex Transcoder Operation Flowchart ................................................................ 49
CVSD 16kbps Frequency Response ............................................................................ 59
CVSD 32kbps Frequency Response ............................................................................ 59
C-BUS Timing ............................................................................................................... 60
PCM Internal Clock Timings ......................................................................................... 61
PCM External Clock Timings ........................................................................................ 62
Mechanical Outline of 64-pin VQFN (Q1) ..................................................................... 63
Mechanical Outline of 64-pin LQFP (L9) ....................................................................... 63
Information in this data sheet should not be relied upon for final product design. It is always recommended
that you check for the latest product datasheet version from the CML website: [www.cmlmicro.com].
1.1
History
Changes
Added availability of L9 package
Added analogue input multiplexer.
Updated analogue output multiplexer.
Added differential speaker driver output.
Added single ended analogue input.
Added independent coarse gain control for ANAOUT, MONOUT and SPKR.
Added Reg Done Select register to provide host handshake.
Added programming register to enable/disable GPIO bus-hold function.
Added programming register to enable/disable core voltage regulator.
Updated C-BUS Timing information to show C-BUS usage at 10MHz clock speed.
Advice in section 5.6 greyed out as not implemented in current FI.
Added advice about terminating unconnected GPIO pins in section 5.6
Updated G.729A current consumption figures, to reflect optimisations done on the
G.729A algorithm.
Documented the SSOUT0 pin which is used when booting from external serial
memory. This pin replaces GPIOD.
Removed the BOOTEN1,2 = 00 reset mechanism as it could be unreliable
Date
13/3/12
7/12/11
Version
9
8
7
6
5
22/08/11
17/08/11
27/07/11
4
08/04/11
2012 CML Microsystems Plc
Page 5
D/7261_FI-1.x/9
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