MOTOROLA
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
Order this document by:
DSP96002/D, Rev. 2
DSP96002
32-BIT GENERAL PURPOSE FLOATING-POINT DUAL-PORT
PROCESSOR
The DSP96002 is designed to support intensive graphic image and numeric processing. It is
a dual-port, low-power, general purpose floating-point processor. The DSP includes 1024
words of data RAM (equally divided into X data and Y data memory), 1024 words of full-
speed on-chip Program RAM, two data ROMs, a dual-channel Direct Memory Access (DMA)
controller, special on-chip bootstrap hardware, and On-Chip Emulation (OnCE™) debug
circuitry. The Central Processing Unit (CPU) consists of three 32-bit execution units
operating in parallel. The DSP96002 has two identical memory expansion ports with control
lines to facilitate interfacing SRAMs, DRAMs (operating in their fast access modes), and
Video RAMs (VRAMs). Each port can be configured as a Host Interface (HI), which
facilitates easy interface with other processors for multiprocessor applications. Linear arrays
of DSP96002s can be implemented without glue logic. The MPU-style programming model
and instruction set allow straightforward generation of efficient, compact code. The high
speed of the DSP96002 makes it well-suited for high bandwidth and numerically intensive
applications that require floating-point processing and access to large memory subsystems.
Control
18
Control
18
Freescale Semiconductor, Inc...
Bus
Control
Address
Generation
Unit (AGU)
YAB *
XAB *
PAB *
Program *
X Data *
Memory
Memory
1024
×
32 512
×
32
RAM and
RAM
64
×
32
Bootstrap
512
×
32†
ROM
ROM
Instruction
Cache
DDB
YDB
XDB
PDB
GDB
Y Data *
Memory
512
×
32
RAM
512
×
32†
ROM
Bus
Control
Address
External
32
Address
Switch
Dual Channel
DMA
Controller
Internal
Switch And Bit
Manipulation
Unit
External Address
32
Address
Switch
4
Port B
32
Data
AA0306
Port A
4
32-bit
Host
Interface
Timer
External
Data
Bus
Switch
32-bit
Host
Interface
Timer
External
Data
Bus
Switch
32
Data
Clock
Generator
Program
Decode
Controller
Program
Address
Generator
Program Controller
Program
Interrupt
Controller
OnCE
Data ALU
Debug
• IEEE Floating Point Controller
• 32
×
32 Integer ALU
4
Serial Debug
Port
CLK
32-bit Buses
* Dual Access (DMA/Core)
† 1024
×
32 Virtual Locations
MODC/IRQC
MODB/IRQB
MODA/IRQA
RESET
Figure 1
Block Diagram
©1996 MOTOROLA, INC.
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
TABLE OF CONTENTS
SECTION 1
SECTION 2
SECTION 3
SECTION 4
SECTION 5
SIGNAL/CONNECTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 1-1
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
BOOTSTRAP CODE FOR DSP96002. . . . . . . . . . . . . . . . . . . . . A-1
X AND Y MEMORY ROM TABLES . . . . . . . . . . . . . . . . . . . . . . . B-1
FOR TECHNICAL ASSISTANCE:
Telephone:
Email:
Internet:
Freescale Semiconductor, Inc...
APPENDIX A
APPENDIX B
1-800-521-6274
dsphelp@dsp.sps.mot.com
http://www.motorola-dsp.com
Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR
“asserted”
“deasserted”
Examples:
Used to indicate a signal that is active when pulled low (For example, the RESET
pin is active when low.)
Means that a high true (active high) signal is high or that a low true (active low)
signal is low
Means that a high true (active high) signal is low or that a low true (active low)
signal is high
Signal/Symbol
PIN
PIN
PIN
PIN
Note:
Logic State
True
False
True
False
Signal State
Asserted
Deasserted
Asserted
Deasserted
Voltage
V
IL
/V
OL
V
IH
/V
OH
V
IH
/V
OH
V
IL
/V
OL
Values for V
IL
, V
OL
, V
IH
, and V
OH
are defined by individual product specifications.
ii
DSP96002/D, Rev. 2
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
DSP96002
Features
FEATURES
•
Digital signal processing core
–
–
–
–
Efficient 32-bit DSP engine
Conforms to IEEE 754-1985 standard for single precision (32-bit) and single
extended precision (44-bit) arithmetic
Up to 30 Million Instructions Per Second (MIPS) at 60 MHz
Parallel operation of Data ALU, Address Generation Unit (AGU), and program
controller within the CPU allow more processing per instruction cycle
Single-cycle 32
×
32 bit parallel multiplier
Highly parallel instruction set with unique DSP addressing modes
Nested hardware DO loops
Instruction cache extended to operate as 4 K byte (1 K word)
Fast auto-return interrupts
Address buses:
•
•
•
•
–
One 32-bit unidirectional internal X memory Address Bus (XAB)
One 32-bit unidirectional internal Y memory Address Bus (YAB)
One 32-bit internal Program Address Bus (PAB)
Two 32-bit external address buses
Freescale Semiconductor, Inc...
–
–
–
–
–
–
Data buses:
•
•
•
•
•
•
One 32-bit bidirectional internal X memory Data Bus (XDB)
One 32-bit bidirectional internal Y memory Data Bus (YDB)
One 32-bit bidirectional internal Global memory Data Bus (GDB)
One 32-bit bidirectional internal DMA Data Bus (DDB)
One 32-bit bidirectional internal Program Data Bus (PDB)
Two 32-bit external data buses
–
•
MCU-like instruction set mnemonics make programming easier
On-chip 1024
×
32-bit Program RAM
Two independent on-chip 512
×
32-bit data RAMs
Two independent on-chip 512
×
32-bit data ROMs (1024
×
32-bit virtual memory)
On-chip 64
×
32-bit bootstrap ROM
Memory
–
–
–
–
MOTOROLA
DSP96002/DRev. 2
For More Information On This Product,
Go to: www.freescale.com
iii
Freescale Semiconductor, Inc.
DSP96002
Product Documentation
–
–
•
Off-chip expansion to 2
×
2
32
32-bit words of data memory
Off-chip expansion to 2
32
32-bit words of program memory
Miscellaneous features
–
–
Two expansion ports assignable to X data, Y data, or program memory spaces or
a combination thereof, effectively doubling off-chip bus bandwidth.
Host interface circuitry on each port provides a flexible slave interface to Direct
Memory Access (DMA) controllers and external processors for easy design of
multimaster systems
Write strobe pins support interface to external SRAMs without additional logic
Two programmable timers/counters
Three external interrupt/mode control lines
One external reset line for hardware reset
4-pin OnCE port for unobtrusive, processor speed-independent debugging
HCMOS design for operating frequencies from 60 MHz down to DC
223-pin plastic Pin Grid Array (PGA) package or 240-pin Ceramic Quad Flat Pack
(CQFP) package
5.0 V power supply
–
Freescale Semiconductor, Inc...
–
–
–
–
–
–
–
PRODUCT DOCUMENTATION
The two manuals listed in
Table 1
are required for a complete description of the DSP96002
and are necessary to design properly with the device. Documentation is available from a
local Motorola distributor, a Motorola semiconductor sales office, a Motorola Literature
Distribution Center, or through the Motorola DSP home page on the Internet (the source for
the latest information).
Table 1
Additional Documentation
Document Name
DSP96002 User’s Manual
DSP96002 Data Sheet
Description
Detailed description of the DSP96002 core
processor and peripherals
Electrical and timing specifications, and pin and
package descriptions
Order Number
DSP96002UM/AD
DSP96002/D
iv
DSP96002/DRev. 2
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
SECTION 1
SIGNAL/CONNECTION DESCRIPTIONS
SIGNAL GROUPINGS
Freescale Semiconductor, Inc...
The input and output signals of the DSP96002 are organized into eight functional
groups, as shown in
Table 1-1
and as illustrated in
Figure 1-1
.
Table 1-1
DSP96002 Functional Signal Groupings
Functional Group
Power (V
CCN
and V
CCQ
)
Ground (GND
N
and GND
Q
)
Clock (CLK)
Interrupt and Mode Control
Port A (Address, Data, and Control)
Port B (Address, Data, and Control)
Timer/Event Counters
OnCE Port
Detailed
Description
Table 1-2
Table 1-3
Table 1-4
Table 1-5
Table 1-6
Table 1-6
Table 1-7
Table 1-8
Figure 1-1
is a diagram of DSP96002 signals by functional group.
MOTOROLA
DSP96002/D, Rev. 2
For More Information On This Product,
Go to: www.freescale.com
1-1
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
