256Kx16 Bit High Speed Static RAM(5V Operating), Revolutionary Pin out.
Operated at Commercial, Extended and Industrial Temperature Ranges.
CMOS SRAM
Revision History
Rev No.
Rev. 0.0
Rev. 0.5
History
Initial release with Design Target.
Release to Preliminary Data Sheet.
0.1. Replace Design Target to Preliminary.
0.2. Delete 12ns part but add 17ns part.
0.3. Relax D.C and A.C parameters and insert new parameter(Icc
1
)
with the test condition.
0.3.1. Insert Icc
1
parameter with the test condition as address is
increased with binary count.
0.3.2. Relax D.C and A.C parameters.
Previous spec.
Relaxed spec.
Items
(15/ - /20ns part)
(15/17/20ns part)
Icc
250/ - /240mA
280/275/270mA
t
CW
10/ - /12ns
12/13/14ns
t
AW
10/ - /12ns
12/13/14ns
t
WP
(OE=H)
10/ - /12ns
12/13/14ns
t
WP1
(OE=L)
12/ - /14ns
15/17/20ns
t
DW
7/ - /9ns
8/ 9/10ns
Release to Final Data Sheet.
1.1. Delete Preliminary.
1.2. Delete Icc1 parameter with the test condition.
1.3. Update D.C parameters.
Previous spec.
Updated spec.
Items
(15/17/20ns part)
(15/17/20ns part)
Icc
280/275/270mA
210/205/200mA
1.4. Add the test condition for V
OH1
with Vcc=5V±5% at 25°C.
1.5. Add timing diagram to define t
WP1
as
″(Timing
Wave Form of
Write Cycle(OE=Low fixed)″.
2.1 Add extended and industrial temperature range parts.
Add 44-TSOP2 Package.
Draft Data
Jun. 14th, 1996
Sep. 16th, 1996
Remark
Design Target
Preliminary
Rev. 1.0
Jun. 5th, 1997
Final
Rev.2.0
Rev.2.1
Feb. 25th, 1998
Dec. 14th, 1998
Final
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Rev 2.1
December 1998
PRELIMINARY
KM6164002A, KM6164002AE, KM6164002AI
256K x 16 Bit High-Speed CMOS Static RAM
FEATURES
• Fast Access Time 15, 17, 20ns(Max.)
• Low Power Dissipation
Standby (TTL)
: 50mA(Max.)
(CMOS) : 10mA(Max.)
Operating KM6164002A - 15 : 210mA(Max.)
KM6164002A - 17 : 205mA(Max.)
KM6164002A - 20 : 200mA(Max.)
• Single 5.0V±10% Power Supply
• TTL Compatible Inputs and Outputs
• I/O Compatible with 3.3V Devices
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Center Power/Ground Pin Configuration
• Data Byte Control ; LB: I/O
1
~ I/O
8,
UB: I/O
9
~ I/O
16
• Standard Pin Configuration
KM6164002AJ : 44-SOJ-400
KM6164002AT : 44-TSOP2-400F
CMOS SRAM
GENERAL DESCRIPTION
The KM6164002A is a 4,194,304-bit high-speed Static Ran-
dom Access Memory organized as 262,144 words by 16 bits.
The KM6164002A uses 16 common input and output lines and
has an output enable pin which operates faster than address
access time at read cycle. Also it allows that lower and upper
byte access by data byte control(UB, LB). The device is fabri-
cated using SAMSUNG′s advanced CMOS process and
designed for high-speed circuit technology. It is particularly well
suited for use in high-density high-speed system applications.
The KM6164002A is packaged in a 400mil 44-pin plastic SOJ
or TSOP(II) forward.
PIN CONFIGURATION
(Top View)
A
0
A
1
A
2
A
3
A
4
CS
I/O
1
I/O
2
I/O
3
1
2
3
4
5
6
7
8
9
44 A
17
43 A
16
42 A
15
41 OE
40 UB
39 LB
38 I/O
16
37 I/O
15
36 I/O
14
ORDERING INFORMATION
KM6164002A-15/17/20
KM6164002AE-15/17/20
KM6164002AI-15/17/20
Commercial Temp.
Extended Temp.
Industrial Temp.
I/O
4
10
FUNCTIONAL BLOCK DIAGRAM
Vcc 11
Vss 12
I/O
5
13
I/O
6
14
SOJ/
TSOP2
35 I/O
13
34 Vss
33 Vcc
32 I/O
12
31 I/O
11
30 I/O
10
29 I/O
9
28 N.C
27 A
14
26 A
13
25 A
12
24 A
11
23 A
10
Clk Gen.
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
I/O
1
~I/O
8
I/O
9
~I/O
16
Pre-Charge Circuit
I/O
7
15
I/O
8
16
WE 17
A
5
18
Row Select
Memory Array
1024 Rows
256x16 Columns
A
6
19
A
7
20
A
8
21
A
9
22
Data
Cont.
Data
Cont.
Gen.
CLK
A
10
I/O Circuit &
Column Select
PIN FUNCTION
Pin Name
A
0
- A
17
Pin Function
Address Inputs
Write Enable
Chip Select
Output Enable
Lower-byte Control(I/O
1
~I/O
8
)
Upper-byte Control(I/O
9
~I/O
16
)
Data Inputs/Outputs
Power(+5.0V)
Ground
No Connection
A
11
A
12
A
13
A
15
A
14
A
16
A
17
WE
CS
OE
LB
WE
OE
UB
LB
CS
UB
I/O
1
~ I/O
16
V
CC
V
SS
N.C
-2-
Rev 2.1
December 1998
PRELIMINARY
KM6164002A, KM6164002AE, KM6164002AI
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on Any Pin Relative to V
SS
Voltage on V
CC
Supply Relative to V
SS
Power Dissipation
Storage Temperature
Operating Temperature
Commercial
Extended
Industrial
Symbol
V
IN
, V
OUT
V
CC
P
D
T
STG
T
A
T
A
T
A
Rating
-0.5 to 7.0
-0.5 to 7.0
1.0
-65 to 150
0 to 70
-25 to 85
-40 to 85
Unit
V
V
W
°C
°C
°C
°C
CMOS SRAM
*
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS*
(T
A
=0 to 70°C)
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min
4.5
0
2.2
-0.5*
Typ
5.0
0
-
-
Max
5.5
0
V
CC
+ 0.5**
0.8
Unit
V
V
V
V
* The above parameters are also guaranteed at extended and industrial temperature ranges.
**
V
IL
(Min) = -2.0V a.c(Pulse Width
≤
10ns) for I
≤
20mA.
***
V
IH
(Max) = V
CC
+ 2.0V a.c (Pulse Width
≤
10ns) for I
≤
20mA.
DC AND OPERATING CHARACTERISTICS*
(T
A
=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified)
Parameter
Input Leakage Current
Output Leakage Current
Operating Current
Symbol
I
LI
I
LO
I
CC
Test Conditions
V
IN
=V
SS
to V
CC
CS=V
IH
or OE=V
IH
or WE=V
IL
V
OUT
= V
SS
to V
CC
Min. Cycle, 100% Duty
CS=V
IL,
V
IN
=V
IH
or V
IL,
I
OUT
=0mA
15ns
17ns
20ns
Standby Current
I
SB
I
SB1
Output Low Voltage Level
Output High Voltage Level
V
OL
V
OH
Min. Cycle, CS=V
IH
f=0MHz, CS≥V
CC
-0.2V,
V
IN
≥V
CC
-0.2V or V
IN
≤0.2V
I
OL
=8mA
I
OH
=-4mA
Min
-2
-2
-
-
-
-
-
-
2.4
Max
2
2
210
205
200
50
10
0.4
-
mA
mA
V
V
Unit
µA
µA
mA
* The above parameters are also guaranteed at extended and industrial temperature ranges.
CAPACITANCE*
(T
A
=25°C, f=1.0MHz)
Item
Input/Output Capacitance
Input Capacitance
* Capacitance is sampled and not 100% tested.
Symbol
C
I/O
C
IN
Test Conditions
V
I/O
=0V
V
IN
=0V
MIN
-
-
Max
8
7
Unit
pF
pF
-3-
Rev 2.1
December 1998
PRELIMINARY
KM6164002A, KM6164002AE, KM6164002AI
AC CHARACTERISTICS
(T
A
=0 to 70°C, V
CC
=5.0V±10%, unless otherwise noted.)
TEST CONDITIONS*
Parameter
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Reference Levels
Output Loads
* The above parameters are also guaranteed at extended and industrial temperature ranges.
CMOS SRAM
Value
0V to 3V
3ns
1.5V
See below
Output Loads(A)
+5.0V
480Ω
D
OUT
255Ω
30pF*
Output Loads(B)
for t
HZ
, t
LZ
, t
WHZ
, t
OW
, t
OLZ
& t
OHZ
+5.0V
480Ω
D
OUT
255Ω
5pF*
* Including Scope and Jig Capacitance
READ CYCLE*
Parameter
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
UB, LB Access Time
Chip Enable to Low-Z Output
Output Enable to Low-Z Output
UB, LB Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
UB, LB Disable to High-Z Output
Output Hold from Address Change
Symbol
t
RC
t
AA
t
CO
t
OE
t
BA
t
LZ
t
OLZ
t
BLZ
t
HZ
t
OHZ
t
BHZ
t
OH
KM6164002A-15
Min
15
-
-
-
-
3
0
0
0
0
0
3
Max
-
15
15
7
7
-
-
-
7
7
7
-
KM6164002A-17
Min
17
-
-
-
-
3
0
0
0
0
0
3
Max
-
17
17
8
8
-
-
-
8
8
8
-
KM6164002A-20
Min
20
-
-
-
-
3
0
0
0
0
0
3
Max
-
20
20
9
9
-
-
-
9
9
9
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
* The above parameters are also guaranteed at extended and industrial temperature ranges.
-4-
Rev 2.1
December 1998
PRELIMINARY
KM6164002A, KM6164002AE, KM6164002AI
WRITE CYCLE*
Parameter
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
Write Pulse Width(OE High)
Write Pulse Width(OE Low)
UB, LB Valid to End of Write
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
Symbol
t
WC
t
CW
t
AS
t
AW
t
WP
t
WP1
t
BW
t
WR
t
WHZ
t
DW
t
DH
t
OW
KM6164002A-15
Min
15
12
0
12
12
15
12
0
0
8
0
3
Max
-
-
-
-
-
-
-
-
7
-
-
-
KM6164002A-17
Min
17
13
0
13
13
17
13
0
0
9
0
3
Max
-
-
-
-
-
-
-
-
8
-
-
-
KM6164002A-20
Min
20
14
0
14
14
20
14
0
0
10
0
3
Max
-
-
-
-
-
-
-
-
9
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CMOS SRAM
* The above parameters are also guaranteed at extended and industrial temperature ranges.
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