74LVC2G125
Dual bus buffer/line driver; 3-state
Rev. 11 — 9 September 2010
Product data sheet
1. General description
The 74LVC2G125 provides a dual non-inverting buffer/line driver with 3-state output.
The 3-state output is controlled by the output enable input (pin nOE). A HIGH-level at pin
nOE causes the output to assume a high-impedance OFF-state. Schmitt trigger action at
all inputs makes the circuit highly tolerant of slower input rise and fall times.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
2. Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant input/output for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
±24
mA output drive (V
CC
= 3.0 V)
CMOS low-power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C
NXP Semiconductors
74LVC2G125
Dual bus buffer/line driver; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVC2G125DP
74LVC2G125DC
74LVC2G125GT
74LVC2G125GF
74LVC2G125GD
74LVC2G125GM
74LVC2G125GN
74LVC2G125GS
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
Name
TSSOP8
VSSOP8
XSON8
XSON8
XSON8U
XQFN8U
XSON8
XSON8
Description
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
Version
SOT505-2
Type number
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
plastic extremely thin small outline package; no leads; SOT833-1
8 terminals; body 1
×
1.95
×
0.5 mm
extremely thin small outline package; no leads;
8 terminals; body 1.35
×
1
×
0.5 mm
SOT1089
plastic extremely thin small outline package; no leads; SOT996-2
8 terminals; UTLP based; body 3
×
2
×
0.5 mm
plastic extremely thin quad flat package; no leads;
8 terminals; UTLP based; body 1.6
×
1.6
×
0.5 mm
extremely thin small outline package; no leads;
8 terminals; body 1.2
×
1.0
×
0.35 mm
extremely thin small outline package; no leads;
8 terminals; body 1.35
×
1.0
×
0.35 mm
SOT902-1
SOT1116
SOT1203
4. Marking
Table 2.
Marking codes
Marking code
[1]
V25
V25
V25
VM
V25
V25
VM
VM
Type number
74LVC2G125DP
74LVC2G125DC
74LVC2G125GT
74LVC2G125GF
74LVC2G125GD
74LVC2G125GM
74LVC2G125GN
74LVC2G125GS
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
74LVC2G125
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 11 — 9 September 2010
2 of 22
NXP Semiconductors
74LVC2G125
Dual bus buffer/line driver; 3-state
5. Functional diagram
74LVC2G125
1A
1OE
2A
2OE
EN2
mna941
001aae009
74LVC2G125
1Y
EN1
2Y
2
1
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
6. Pinning information
6.1 Pinning
74LVC2G125
1OE
1
8
V
CC
1A
2
7
2OE
74LVC2G125
1OE
1A
2Y
GND
1
2
3
4
001aab738
8
7
6
5
V
CC
2OE
1Y
2A
2Y
3
6
1Y
GND
4
5
2A
001aab739
Transparent top view
Fig 3.
Pin configuration SOT505-2 and SOT765-1
Fig 4.
Pin configuration SOT833-1, SOT1089,
SOT1116 and SOT1203
74LVC2G125
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 11 — 9 September 2010
3 of 22
NXP Semiconductors
74LVC2G125
Dual bus buffer/line driver; 3-state
74LVC2G125
terminal 1
index area
2OE
1
V
CC
8
74LVC2G125
1OE
1A
2Y
GND
1
2
3
4
8
7
6
5
V
CC
7
1OE
1Y
2OE
1Y
2A
2A
2
6
1A
3
4
5
2Y
GND
001aae010
001aai243
Transparent top view
Transparent top view
Fig 5.
Pin configuration SOT996-2
Fig 6.
Pin configuration SOT902-1
6.2 Pin description
Table 3.
Symbol
Pin description
Pin
SOT505-2, SOT765-1, SOT833-1, SOT1089,
SOT996-2, SOT1116 and SOT1203
1OE, 2OE
1A, 2A
GND
1Y, 2Y
V
CC
1, 7
2, 5
4
6, 3
8
SOT902-1
7, 1
6, 3
4
2, 5
8
output enable input (active LOW)
data input
ground (0 V)
data output
supply voltage
Description
7. Functional description
Table 4.
Control
nOE
L
L
H
[1]
Function table
[1]
Input
nA
L
H
X
Output
nY
L
H
Z
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
74LVC2G125
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 11 — 9 September 2010
4 of 22
NXP Semiconductors
74LVC2G125
Dual bus buffer/line driver; 3-state
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
V
O
> V
CC
or V
O
< 0 V
Enable mode
Disable mode
Power-down mode
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
[1]
[1]
[1][2]
Conditions
V
I
< 0 V
[1]
Min
−0.5
−50
−0.5
-
−0.5
−0.5
−0.5
-
-
−100
−65
Max
+6.5
-
+6.5
±50
V
CC
+ 0.5
+6.5
+6.5
±50
100
-
+150
300
Unit
V
mA
V
mA
V
V
V
mA
mA
mA
°C
mW
output current
supply current
ground current
storage temperature
total power dissipation
V
O
= 0 V to V
CC
T
amb
=
−40 °C
to +125
°C
[3]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
When V
CC
= 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
For TSSOP8 package: above 55
°C
the value of P
tot
derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110
°C
the value of P
tot
derates linearly with 8 mW/K.
For XSON8, XSON8U and XQFN8U packages: above 118
°C
the value of P
tot
derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
V
CC
V
I
V
O
Operating conditions
Parameter
supply voltage
input voltage
output voltage
V
CC
= 1.65 V to 5.5 V; Enable mode
V
CC
= 1.65 V to 5.5 V; Disable mode
V
CC
= 0 V; Power-down mode
T
amb
Δt/ΔV
ambient temperature
input transition rise and V
CC
= 1.65 V to 2.7 V
fall rate
V
CC
= 2.7 V to 5.5 V
Conditions
Min
1.65
0
0
0
0
−40
-
-
Max
5.5
5.5
V
CC
5.5
5.5
+125
20
10
Unit
V
V
V
V
V
°C
ns/V
ns/V
74LVC2G125
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 11 — 9 September 2010
5 of 22
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