PRELIMINARY
FEMTOCLOCKS™ DUAL VCXO VIDEO PLL
ICS810001-21
Features
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Accepts various HD and SD references including hsync,
transport and pixel clock rates
Outputs HD and SD pixel rates
One LVCMOS/LVTTL PLL clock output
Two selectable LVCMOS/LVTTL input clocks
LVCMOS input select lines
VCXO PLL bandwidth can be optimized for jitter attenuation and
reference tracking
FemtoClock frequency multiplier provides low jitter, high
frequency output
FemtoClock range: 560MHz - 700MHz
RMS phase jitter @148.3516484MHz, using a 26.973027MHz
crystal (12kHz - 20MHz): 1.089ps (typical)
3.3V supply voltage
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
General Description
The ICS810001-21 is a member of the HiperClockS™
family of high performance clock solutions from IDT.
HiPerClockS™
The ICS810001-21 is a PLL based synchronous
clock generator that is optimized for digital video
clock jitter attenuation and frequency translation.
The device contains two internal frequency multiplication stages
that are cascaded in series. The first stage is a VCXO PLL that is
optimized to provide reference clock jitter attenuation, and to
support the complex PLL multiplication ratios needed for video
rate conversion. The second stage is a FemtoClock frequency
multiplier that provides the low jitter, high frequency video output
clock.
ICS
Preset multiplication ratios are selected from internal lookup
tables using device input selection pins. The multiplication ratios
are optimized to support most common video rates used in
professional video system applications. The VCXO requires the
use of an external, inexpensive pullable crystal. Two crystal
connections are provided (pin selectable) so that both 60 and
59.94 base frame rates can be supported. The VCXO requires
external passive loop filter components which are used to set the
PLL loop bandwidth and damping characteristics.
Output Rates Supported
Frequency (MHz)
27
26.973027
74.25
74.17582418
148.5
148.3516484
36
Application
Pin Assignment
XTAL_OUT0
XTAL_OUT1
XTAL_IN0
XTAL_IN1
GND
XTAL_SEL
V
DDX
MPEG Transport, ITU-R601, CCIR 656
27MHz x 1000/1001
SMPTE 292M/60
LF1
1
2
3
4
5
6
7
8
9
CLK0
32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
10 11 12 13 14 15 16
V2
V0
V
DD
MR
MF
V1
V3
V
DD
N0
N1
nBP1
OE
GND
Q
V
DDO
V
DDA
SMPTE 292M/59.94
SMPTE 292M/60, 1080P
SMPTE 292M/59.94, 1080P
SMPTE 292M Level “D”
LF0
ISET
V
DD
nBP0
GND
CLK_SEL
Example Frequency Conversions:
All nine combinations from/to:
27MHz
74.175MHz
74.25MHz
NTSC or PAL hsync to 27MHz
NTSC or PAL hsync to 4xFsc
CLK1
ICS810001-21
32 Lead VFQFN
5mm x 5mm x 0.925mm package body
K Package
Top View
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™
DUAL VCXO VIDEO PLL
1
ICS810001DK-21 REV. C
OCTOBER 8, 2008
ICS810001-21
FEMTOCLOCKS™ DUAL VCXO VIDEO PLL
PRELIMINARY
Table 1. Pin Descriptions
Number
1, 2
3
4, 11, 25
5, 22
6, 20, 29
7
8, 9
10, 14,
15, 16
12
13
17
18
19
21
23, 24
26
27,
28
30,
31
32
Name
LF1, LF0
ISET
V
DD
nBP0,
nBP1
GND
CLK_SEL
CLK1, CLK0
V0, V1,
V2, V3
MR
MF
V
DDA
V
DDO
Q
OE
N1, N0
XTAL_SEL
XTAL_OUT1,
XTAL_IN1
XTAL_OUT0,
XTAL_IN0
V
DDX
Type
Analog
Input/Output
Analog
Input/Output
Power
Input
Power
Input
Input
Input
Pulldown
Pulldown
Pulldown
Pullup
Description
Loop filter connection node pins.
Charge pump current setting pin.
Core supply pins.
PLL Bypass control pins. See block diagram.
Power supply ground.
Input clock select. When HIGH selects CLK1. When LOW, selects CLK0.
LVCMOS / LVTTL interface levels.
Single-ended clock inputs. LVCMOS/LVTTL interface levels.
VCXO PLL divider selection pins. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the output to go low. When logic LOW, the internal dividers and the
output is enabled. LVCMOS/LVTTL interface levels.
FemtoClock multiplication factor select pin. LVCMOS/LVTTL interface levels.
Analog supply pin.
Output supply pin.
Single-ended VCXO PLL clock output. LVCMOS/LVTTL interface levels.
Pullup
Pulldown
Pulldown
Output enable. When logic LOW, the clock output is in high impedance. When
logic HIGH, the output is enabled. LVCMOS/LVTTL interface levels.
FemtoClock output divide select pins. LVCMOS/LVTTL interface levels.
Crystal select. When HIGH, selects XTAL1. When LOW, selects XTAL0.
LVCMOS/LVTTL interface levels.
Crystal oscillator interface. XTAL_IN1 is the input. XTAL_OUT1 is the output.
Crystal oscillator interface. XTAL_IN0 is the input. XTAL_OUT0 is the output.
Power supply pin for VCXO charge pump.
Input
Input
Power
Power
Output
Input
Input
Input
Input
Input
Power
Pulldown
Pulldown
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
Input Pulldown Resistor
V
DD
= V
DDO
= 3.465V
51
51
Test Conditions
Minimum
Typical
4
Maximum
Units
pF
pF
k
Ω
k
Ω
IDT™ / ICS™
DUAL VCXO VIDEO PLL
3
ICS810001DK-21 REV. C
OCTOBER 8, 2008
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