three-state drivers. The device has an automatic power-down
feature (CE
1
), reducing the power consumption by over 70%
when deselected. The CY7C185A is in the standard
300-mil-wide DIP package and leadless chip carrier.
Writing to the device is accomplished when the Chip Enable
one (CE
1
) and Write Enable (WE) inputs are both LOW, and
the Chip Enable two (CE
2
) input is HIGH.
Data on the eight I/O pins (I/O
0
through I/O
7
) is written into the
memory location specified on the address pins (A
0
through
A
12
).
Reading the device is accomplished by taking Chip Enable
one (CE
1
) and Output Enable (OE) LOW, while taking Write
Enable (WE) and Chip Enable two (CE
2
) HIGH. Under these
conditions, the contents of the memory location specified on
the address pins will appear on the I/O pins.
The I/O pins remain in a high-impedance state when Chip En-
able one (CE
1
) or Output Enable (OE) is HIGH, or Write En-
able (WE) or Chip Enable two (CE
2
) is LOW.
A die coat is used to ensure alpha immunity.
Functional Description
The CY7C185A is a high-performance CMOS static RAM or-
ganized as 8192 words by 8 bits. Easy memory expansion is
provided by an active LOW Chip Enable (CE
1
), an active HIGH
Chip Enable (CE
2
), an active LOW Output Enable (OE), and
Logic Block Diagram
Pin Configurations
DIP
Top View
NC
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
I/O
0
I/O
1
I/O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
CE
2
A
3
A
2
A
1
OE
A
0
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
LCC
Top View
3 2 1 28 27
4
26
5
25
6
24
7
23
8
22
9
21
10
20
11
19
12
18
1314151617
I/O2
GND
I/O3
I/O4
I/O5
C185A–3
A6
A5
A4
VCC
WE
NC
A
7
A
8
A
9
A
10
A
11
A
12
I/O
0
I/O
1
CE
2
A
3
A
2
A
1
OE
A
0
CE
1
I/O
7
I/O
6
I/O
0
INPUT BUFFER
I/O
1
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
ROW DECODER
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
CE
1
CE
2
WE
OE
COLUMN DECODER
POWER
DOWN
8K x 8
ARRA
Y
SENSE AMPS
C185A–2
I/O
7
A
10
A
11
A
12
A
0
A
9
C185A–1
Selection Guide
[1]
7C185A–20
Maximum Access Time (ns)
Maximum Operating Current (mA) Military
Maximum Standby Current (mA)
Military
Note:
1. For commercial specifications, see the CY7C185 data sheet.
7C185A–25
25
125
40/20
7C185A–35
35
125
30/20
7C185A–45
45
125
30/20
20
135
40/20
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
October 4, 1999
CY7C185A
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................. –65°C to +150°C
Ambient Temperature with
Power Applied .............................................. –55°C to +125°C
Supply Voltage to Ground Potential
(Pin 28 to Pin 14) ........................................... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
[2]
.....................................................–0.5V to +7.0V
DC Input Voltage
[2]
................................................. –0.5V to +7.0V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current .................................................... >200 mA
Operating Range
Range
Military
[4]
Ambient
Temperature
[3]
–55
°
C to +125
°
C
V
CC
5V
±
10%
Electrical Characteristics
Over the Operating Range
[4]
7C185A–20
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
I
SB1
I
SB2
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[2]
Input Load Current
Output Leakage Current
Output Short Circuit Current
[5]
V
CC
Operating Supply Current
Automatic CE
1
Power-Down
Current
Automatic CE
1
Power-Down
Current
GND
≤
V
I
≤
V
CC
GND
≤
V
I
≤
V
CC
, Output Disabled
V
CC
= Max., V
OUT
= GND
V
CC
= Max. I
OUT
= 0 mA
Max. V
CC
, CE
1
≥
V
IH,
Min. Duty Cycle = 100%
Max. V
CC
, CE
1
≥
V
CC
–0.3V
V
IN
≥
V
CC
–0.3Vor V
IN
≥
0.3V
Military
Military
Military
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
2.2
–0.5
–10
–10
Min.
2.4
0.4
V
CC
0.8
+10
+10
–300
135
40
20
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
mA
Electrical Characteristics
Over the Operating Range
[4]
(continued)
7C185A–25
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
I
SB1
I
SB2
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[2]
Input Load Current
Output Leakage Current
Output Short
Circuit Current
[5]
V
CC
Operating Supply
Current
Automatic CE
1
Power-Down Current
Automatic CE
1
Power-Down Current
GND
≤
V
I
≤
V
CC
GND
≤
V
I
≤
V
CC
, Output Disabled
V
CC
= Max., V
OUT
= GND
V
CC
= Max., I
OUT
= 0 mA
Max. V
CC
, CE
1
≥
V
IH,
Min. Duty Cycle=100%
Military
Military
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
2.2
–0.5
–10
–10
Min.
2.4
0.4
V
CC
0.8
+10
+10
–300
125
40
20
2.2
–0.5
–10
–10
Max.
7C185A–35, 45
Min.
2.4
0.4
V
CC
0.8
+10
+10
–300
125
30
20
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
mA
Max. V
CC
, CE
1
≥
V
CC
–0.3V Military
V
IN
≥
V
CC
–0.3Vor V
IN
≥
0.3V
Notes:
2. V
IL
(min.) = – 3.0V for pulse durations less than 30 ns.
3. T
A
is the case temperature.
4. See the last page of this specification for Group A subgroup testing information.
5. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
2
CY7C185A
Capacitance
[6]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
10
10
Unit
pF
pF
Note:
6. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
R1 481Ω
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
R2
255Ω
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
R2
255Ω
C185A–4
R1 481Ω
ALL INPUT PULSES
3.0V
10%
GND
≤
5 ns
90%
90%
10%
≤
5 ns
C185A–5
(a)
Equivalent to:
THÉVENIN EQUIVALENT
167Ω
OUTPUT
1.73V
(b)
3
CY7C185A
Switching Characteristics
Over the Operating Range
[7]
7C185A–20
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE1
t
ACE2
t
DOE
t
LZOE
t
HZOE
t
LZCE1
t
LZCE2
t
HZCE
t
PU
t
PD
t
WC
t
SCE1
t
SCE2
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
LOW to Data Valid
CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
[8]
CE
1
LOW to Low Z
[9]
CE
2
HIGH to Low Z
CE
1
HIGH to High Z
[8, 9]
CE
2
LOW to High Z
CE
1
LOW to Power-Up
CE
1
HIGH to Power-Down
Write Cycle Time
CE
1
LOW to Write End
CE
2
HIGH to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
WE LOW to High Z
[8]
20
15
15
15
0
0
15
10
0
3
7
0
20
5
3
8
0
20
3
8
5
3
10
0
20
3
20
20
10
3
10
5
3
15
0
25
20
20
3
25
25
12
3
12
5
3
15
25
25
3
35
35
15
3
15
35
35
3
45
30
20
45
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
7C185A–25
Min.
Max.
7C185A–35
Min.
Max.
7C185A–45
Min.
Max.
Unit
WRITE CYCLE
[10]
20
20
20
20
0
0
15
10
0
5
7
25
25
25
25
0
0
20
15
0
5
10
40
30
30
30
0
0
20
15
0
5
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
8. t
HZOE,
t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in part (b) of AC Test Loads. Transition is measured
±500
mV from steady-state voltage.
9. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
for any given device.
10. Device is continuously selected. OE, CE = V
IL
. CE
2
= V
IH
.
4
CY7C185A
Switching Waveforms
Read Cycle No. 1
[10, 11]
t
RC
ADDRESS
t
OHA
DATA OUT
PREVIOUS DATA VALID
t
AA
DATA VALID
C185A–6
Read Cycle No. 2
[11, 12]
t
RC
CE
1
CE
2
t
ACE
OE
OE
t
DOE
t
LZOE
HIGH IMPEDANCE
t
LZCE
V
CC
SUPPLY
CURRENT
t
PU
50%
t
HZOE
t
HZCE
DATA VALID
t
PD
50%
ISB
C185A–7
HIGH
IMPEDANCE
DATA OUT
ICC
Write Cycle No. 1 (WE Controlled)
[13, 14]
t
WC
ADDRESS
t
SCE1
CE
1
CE
2
t
SCE2
OE
WE
t
SA
t
AW
t
PWE
t
HA
t
SD
DATA IN
t
HZOE
HIGH IMPEDANCE
DATA I/O
DATA UNDEFINED
DATA
IN
VALID
t
HD
t
LZWE
C185A–8
Notes:
11. Address valid prior to or coincident with CE transition LOW.
12. WE is HIGH for read cycle.
13. The internal write time of the memory is defined by the overlap of CE
1
LOW, CE
2
HIGH, and WE LOW. Both signals must be LOW to initiate a write and either signal
can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
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