CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications
V
CC
= 5V
±10%;
T
A
= -40
o
C to +85
o
C (HM-6516B-9, HM-6516-9)
LIMITS
SYMBOL
ICCSB
PARAMETER
Standby Supply Current
MIN
-
MAX
50
UNITS
µA
µA
TEST CONDITIONS
IO = 0mA, VI = V
CC
or GND,
V
CC
= 5.5V, HM-6516B-9
IO = 0mA, VI = V
CC
or GND,
HM-6516-9
f = 1MHz, IO = 0mA, G = V
CC
, V
CC
=
5.5V, VI = V
CC
or GND
V
CC
= 2.0V, IO = 0mA, VI = V
CC
or
GND, E = V
CC
, HM-6516B-9
V
CC
= 2.0V, IO = 0mA, VI = V
CC
or
GND, E = V
CC
, HM-6516-9
-
100
ICCOP
Operating Supply Current (Note 1)
-
10
mA
µA
µA
ICCDR
Data Retention Supply Current
-
25
-
50
VCCDR
II
IIOZ
V
IL
V
IH
VOL
VOH1
VOH2
Data Retention Supply Voltage
Input Leakage Current
Input/Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output High Voltage (Note 2)
2.0
-1.0
-1.0
-0.3
2.4
-
2.4
V
CC
-0.4
-
+1.0
+1.0
0.8
V
CC
+0.3
0.4
-
-
V
µA
µA
V
V
V
V
V
VI = V
CC
or GND, V
CC
= 5.5V
VIO = V
CC
or GND, V
CC
= 5.5V
V
CC
= 4.5V
V
CC
= 5.5V
IO = 3.2mA, V
CC
= 4.5V
IO = -1.0mA, V
CC
= 4.5V
IO = -100µA, V
CC
= 4.5V
Capacitance
T
A
= +25
o
C
SYMBOL
CI
CIO
NOTES:
1. Typical derating 5mA/MHz increase in ICCOP.
2. Tested at initial design and after major design changes.
PARAMETER
Input Capacitance (Note 2)
Input/Output Capacitance (Note 2)
MAX
8
10
UNITS
pF
pF
TEST CONDITIONS
f = 1MHz, All measurements are
referenced to device GND
3
HM-6516
AC Electrical Specifications
V
CC
= 5V
±10%;
T
A
= -40
o
C to +85
o
C (HM-6516B-9, HM-6516-9)
LIMITS
HM-6516B-9
SYMBOL
(1)
TELQV
(2)
TAVQV
(3)
TELQX
(4)
TWLQZ
(5)
TEHQZ
(6)
TGLQV
(7)
TGLQX
(8)
TGHQZ
(9)
TELEH
(10)
TEHEL
(11)
TAVEL
(12)
TELAX
(13)
TWLWH
(14)
TWLEH
(15)
TELWH
(16)
TDVWH
(17)
TWHDX
(18)
TELEL
HM-6516-9
MIN
-
-
10
-
-
-
10
-
200
80
0
50
200
200
200
80
10
280
MAX
200
200
-
80
80
80
-
80
-
-
-
-
-
-
-
-
-
-
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TEST
CONDITIONS
(Notes 1, 3)
(Notes 1, 3, 4)
(Notes 2, 3)
(Notes 2, 3)
(Notes 2, 3)
(Notes 1, 3)
(Notes 2, 3)
(Notes 2, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
PARAMETER
Chip Enable Access Time
Address Access Time
Chip Enable Output Enable Time
Write Enable Output Disable Time
Chip Enable Output Disable Time
Output Enable Output Valid Time
Output Enable Output Enable Time
Output Enable Output DisableTime
Chip Enable Pulse Negative Width
Chip Enable Pulse Positive Width
Address Setup Time
Address Hold Time
Write Enable Pulse Width
Write Enable Pulse Setup Time
Write Enable Pulse Hold Time
Data Setup Time
Data Hold Time
Read or Write Cycle Time
MIN
-
-
10
-
-
-
10
-
120
50
0
30
120
120
120
50
10
170
MAX
120
120
-
50
50
80
-
50
-
-
-
-
-
-
-
-
-
-
NOTES:
1. Input pulse levels: 0.8V to V
CC
- 2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load:
1 TTL gate equivalent, C
L
= 50pF (min) - for C
L
greater than 50pF, access time is derated by 0.15ns per pF.
2. Tested at initial design and after major design changes.
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