CY7C1020D
512-Kbit (32 K × 16) Static RAM
512-Kbit (32 K × 16) Static RAM
Features
■
■
■
■
■
■
Deselected (CE HIGH)
Outputs are disabled (OE HIGH)
BHE and BLE are disabled (BHE, BLE HIGH)
When the write operation is active (CE LOW, and WE LOW)
Pin- and function-compatible with CY7C1020B
High speed
❐
t
AA
= 10 ns
= 80 mA @ 10 ns
■
Low active power
❐
I
CC
■
Low complementary metal oxide semiconductor (CMOS)
standby power
❐
I
SB2
= 3 mA
■
■
■
■
■
2.0 V data retention
Automatic power-down when deselected
CMOS for optimum speed/power
Independent control of upper and lower bits
Available in Pb-free 44-pin 400-Mil wide Molded SOJ and
44-pin thin small outline package (TSOP) II packages
Write to the device by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO
0
through IO
7
), is written into the location
specified on the address pins (A
0
through A
14
). If Byte High
Enable (BHE) is LOW, then data from IO pins (IO
8
through IO
15
)
is written into the location specified on the address pins (A
0
through A
14
).
Reading from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on IO
0
to IO
7
. If
Byte High Enable (BHE) is LOW, then data from memory
appears on IO
8
to IO
15
. See the
“Truth Table” on page 11
for a
complete description of read and write modes.
The CY7C1020D device is suitable for interfacing with
processors that have TTL I/P levels. It is not suitable for
processors that require CMOS I/P levels. Please see
Electrical
Characteristics on page 4
for more details and suggested
alternatives.
For a complete list of related documentation,
click here.
Functional Description
The CY7C1020D
[1]
is a high-performance CMOS static RAM
organized as 32,768 words by 16 bits. This device has an
automatic power-down feature that significantly reduces power
consumption when deselected.The input and output pins
(IO
0
through IO
15
) are placed in a high-impedance state when:
Logic Block Diagram
DATA IN DRIVERS
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
32K x 16
RAM Array
SENSE AMPS
IO
0
–IO
7
IO
8
–IO
15
COLUMN DECODER
BHE
WE
CE
OE
BLE
A
8
A
9
A
10
A
11
A
12
A
13
Note
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at
www.cypress.com.
A
14
Cypress Semiconductor Corporation
Document Number: 38-05463 Rev. *J
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 28, 2014
CY7C1020D
Contents
Pin Configurations ........................................................... 3
Selection Guide ................................................................ 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 11
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagrams .......................................................... 13
Acronyms ........................................................................ 15
Document Conventions ................................................. 15
Units of Measure ....................................................... 15
Document History Page ................................................. 16
Sales, Solutions, and Legal Information ...................... 17
Worldwide Sales and Design Support ....................... 17
Products .................................................................... 17
PSoC® Solutions ...................................................... 17
Cypress Developer Community ................................. 17
Technical Support ..................................................... 17
Document Number: 38-05463 Rev. *J
Page 2 of 17
CY7C1020D
Pin Configurations
Figure 1. 44-pin SOJ/TSOP II pinout (Top View)
[2]
NC
A
3
A
2
A
1
A
0
CE
IO
0
IO
1
IO
2
IO
3
V
CC
V
SS
IO
4
IO
5
IO
6
IO
7
WE
A
4
A
14
A
13
A
12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
5
A
6
A
7
OE
BHE
BLE
IO
15
IO
14
IO
13
IO
12
V
SS
V
CC
IO
11
IO
10
IO
9
IO
8
NC
A
8
A
9
A
10
A
11
NC
Selection Guide
Description
Maximum access time
Maximum operating current
Maximum CMOS standby current
-10 (Industrial)
10
80
3
Unit
ns
mA
mA
Note
2. NC pins are not connected on the die.
Document Number: 38-05463 Rev. *J
Page 3 of 17
CY7C1020D
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65
C
to +150
C
Ambient temperature with
power applied .......................................... –55
C
to +125
C
Supply voltage on
V
CC
to Relative GND
[3]
...............................–0.5 V to +6.0 V
DC voltage applied to outputs
in High Z State
[3]
................................ –0.5 V to V
CC
+ 0.5 V
DC input voltage
[3]
............................. –0.5 V to V
CC
+ 0.5 V
Current into outputs (LOW) ........................................ 20 mA
Static discharge voltage
(per MIL-STD-883, Method 3015) ........................... >2001 V
Latch-up current ..................................................... >200 mA
Operating Range
Range
Industrial
Ambient
Temperature
–40 °C to +85 °C
V
CC
5 V
0.5 V
Speed
10 ns
Electrical Characteristics
Over the Operating Range
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Output HIGH voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
[3]
Input load current
Output leakage current
V
CC
operating supply current
I
OH
= –4.0 mA
I
OH
= –0.1 mA
I
OL
= 8.0 mA
–
–
GND < V
I
< V
CC
GND < V
I
< V
CC
, output disabled
V
CC
= Max, I
OUT
= 0 mA,
f = f
max
= 1/t
RC
100 MHz
83 MHz
66 MHz
40 MHz
I
SB1
I
SB2
Automatic CE power-down
current – TTL inputs
Automatic CE Power-Down
current – CMOS inputs
Max V
CC
, CE > V
IH
V
IN
> V
IH
or V
IN
< V
IL
, f = f
max
Max V
CC
, CE > V
CC
– 0.3 V,
V
IN
> V
CC
– 0.3 V, or V
IN
< 0.3 V, f = 0
Test Conditions
-10 (Industrial)
Min
2.4
–
–
2.2
–0.5
–1
–1
–
–
–
–
–
–
Max
–
3.4
[4]
0.4
V
CC
+ 0.5
0.8
+1
+1
80
72
58
37
10
3
V
V
V
A
A
mA
mA
mA
mA
mA
mA
Unit
V
Note
3. V
IL
(min) = –2.0 V and V
IH
(max) = V
CC
+ 1 V for pulse durations of less than 5 ns.
4. Please note that the maximum V
OH
limit does not exceed minimum CMOS V
IH
of 3.5V. If you are interfacing this SRAM with 5V legacy processors that require a
minimum V
IH
of 3.5V, please refer to Application Note
AN6081
for technical details and options you may consider.
Document Number: 38-05463 Rev. *J
Page 4 of 17
CY7C1020D
Capacitance
Parameter
C
IN
C
OUT
[5]
Description
Input capacitance
Output capacitance
Test Conditions
T
A
= 25
C,
f = 1 MHz, V
CC
= 5.0 V
Max
8
8
Unit
pF
pF
Thermal Resistance
Parameter
JA
JC
[5]
Description
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to case)
Test Conditions
Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
SOJ
59.52
36.75
TSOP II
53.91
21.24
Unit
C/W
C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
[6]
ALL INPUT PULSES
90%
10%
90%
10%
Z = 50
OUTPUT
50
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
1.5V
3.0V
30 pF*
GND
Rise Time:
3
ns
(a)
High-Z characteristics:
5V
OUTPUT
INCLUDING
JIG AND
SCOPE
5 pF
(b)
Fall Time:
3
ns
R1 480
R2
255
(c)
Notes
5. Tested initially and after any design or process changes that may affect these parameters.
6. AC characteristics (except High-Z) are tested using the load conditions shown in
Figure 2
(a). High-Z characteristics are tested for all speeds using the test load shown
in
Figure 2
(c).
Document Number: 38-05463 Rev. *J
Page 5 of 17
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