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THS1240
12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS279D – JUNE 2000 – REVISED JANUARY 2001
features
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
48 PHP PACKAGE
(TOP VIEW)
applications
Wireless Local Loop
Wireless Internet Access
Cable Modem Receivers
Medical Ultrasound
Magnetic Resonant Imaging
description
The THS1240 is a high-speed low noise 12-bit CMOS pipelined analog-to-digital converter. A differential sample
and hold minimizes even order harmonics and allows for a high degree of common mode rejection at the analog
input. A buffered analog input enables operation with a constant analog input impedance, and prevents transient
voltage spikes from feeding backward to the analog input source. Full temperature DNL performance allows
for industrial application with the assurance of no missing codes. The THS1240 can operate with either internal
or external references. Internal reference usage selection is accomplished simply by externally connecting
reference output terminals to reference input terminals.
AVAILABLE OPTIONS
PACKAGE
TA
– 40°C to 85°C
0°C to 70°C
48-TQFP
(PHP)
THS1240I
THS1240C
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
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DV SS
CLK+
CLK–
DV DD
DV SS
DV SS
DV DD
DV SS
DV DD
DRVSS
DRVDD
AV SS
40-MSPS Sample Rate
12-Bit Resolution
No Missing Codes
On-Chip Sample and Hold
77-dB Spurious Free Dynamic Range at
f
IN
= 15.5 MHz
5-V Analog and Digital Supply
3-V and 5-V CMOS Compatible Digital
Output
10.4 Bit ENOB at f
IN
= 31 MHz
65 dB SNR at f
IN
= 15.5 MHz
120-MHz Bandwidth
Internal or External Reference
Buffered Differential Analog Input
2s Complement Digital Outputs
Typical 380 mW Power Consumption
Single-Ended or Differential Low-Level
Clock Input
48 47 46 45 44 43 42 41 40 39 38 37
AVSS
AVDD
AVSS
AVDD
AVSS
AVSS
DRVSS
DRVSS
DRVDD
DRVDD
VCM
AVDD
AV
SS
AV
DD
V
IN+
V
IN–
AV
DD
V
REFOUT–
V
REFIN
–
V
REFIN
+
V
REFOUT
+
V
BG
AV
SS
AV
DD
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
36
35
34
33
32
31
30
29
28
27
26
25
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
1
THS1240
12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS279D – JUNE 2000 – REVISED JANUARY 2001
functional block diagram
AVDD DVDD DRVDD
VIN+
Buffer
1 kΩ
VIN–
A/D
D/A
Stage 1
S/H
Stages 2 – 9
Stage 10
Stage 11
Σ
A/D
D/A
Σ
1
Digital Error Correction
A/D
VREFIN+
VREFOUT+
VREFOUT–
VREFIN–
VCM
CLK+
1
3.0 V
Reference
AVDD/2
2.0 V
2
Timing
CLK–
AVSS
DVSS DRVSS
D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Terminal Functions
TERMINAL
NAME
AVDD
AVSS
CLK+
CLK–
D11–D0
DRVDD
DRVSS
DVDD
DVSS
VBG
VCM
VIN+
VIN–
VREFIN –
VREFIN+
VREFOUT+
VREFOUT –
NO.
2, 5, 12, 43,
45, 47
1, 11, 13, 41,
42, 44, 46
15
16
25–36
24, 37, 38
23, 39, 40
17, 20, 22
18, 19, 21
10
48
3
4
7
8
9
6
I/O
I
I
I
I
O
I
I
I
I
O
O
I
I
I
I
O
O
Analog power supply
Analog ground return for internal analog circuitry
Clock input
Complementary clock input
Digital data output bits; LSB= D0, MSB = D11 (2s complement output format)
Digital output driver supply
Digital output driver ground return
Positive digital supply
Digital ground return
Band gap reference. Bypass to ground with a 1-µF and a 0.01-µF chip capacitor.
Common mode voltage output. Bypass to ground with a 0.1-µF and a 0.01-µF chip capacitor.
Analog signal input
Complementary analog signal input
External reference input low
External reference input high
Internal reference output. Compensate with a 1-µF and a 0.01-µF chip capacitor.
Internal reference output. Compensate with a 1-µF and a 0.01-µF chip capacitor.
DESCRIPTION
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
THS1240
12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS279D – JUNE 2000 – REVISED JANUARY 2001
functional description
The THS1240 uses a differential pipeline architecture and assures no missing codes over the full operating
temperature range. The device uses a 1 bit per stage architecture in order to achieve the highest possible
bandwidth. The differential analog inputs are terminated with a 1-kΩ resistor. The inputs are then fed to a unity
gain buffer followed by the S/H (sample and hold) stage. This S/H stage is a switched capacitor operational
amplifier-based circuit, see Figure 3. The pipeline is a typical 1 bit per stage pipeline as shown in the functional
block diagram. The digital output of the 12 stages is sent to a digital correction logic block which then outputs
the final 12 bits.
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
†
Supply voltage range: AV
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
DV
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
DRV
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Voltage between AV
SS
and DV
SS
and DRV
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 0.5 V
Voltage between DRV
DD
and DV
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 5 V
Voltage between AV
DD
and DV
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 5 V
Digital data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to DV
DD
+ 0.3 V
CLK peak input current, I
p(CLK)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Peak total input current (all inputs), I
p
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 30 mA
Operating free-air temperature range, T
A
: THS1240C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
THS1240I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed
under absolute maximum ratings
may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under
recommended operating conditions
is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN
Sample rate
Analog supply voltage, AVDD
Digital supply voltage, DVDD
Digital output driver supply voltage, DRVDD
CLK + high level input voltage, VIH‡
CLK + low-level input voltage, VIL‡
CLK pulse-width high, tp(H)
CLK pulse-width low, tp(L)
Operating free-air temperature range, TA
free air
range
THS1240C
THS1240I
1
4.75
4.75
3
3.5
0
10
10
0
– 40
12.5
12.5
70
85
5
5
3.3
5
NOM
MAX
40
5.25
5.25
5.25
5.25
1.5
UNIT
MSPS
V
V
V
V
V
ns
ns
°C
‡ CLK– Input tied to ground with 0.01
µF
capacitor for single-ended clock source.
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3
THS1240
12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS279D – JUNE 2000 – REVISED JANUARY 2001
electrical characteristics over recommended operating free-air temperature range,
AV
DD
= DV
DD
= 5 V, DRV
DD
= 3.3 V, internal references, CLK = 40 MHz, single-ended clock source
at 40 MHz with 50% duty cycle (unless otherwise noted)
dc accuracy
PARAMETER
DNL
INL
Differential nonlinearity
No missing codes
Integral nonlinearity
EO
Offset error
EG
Gain error
† All typical values are at TA = 25°C.
fIN = 15.5 MHz
V(VIN+) = V(VIN_) = VCM
TEST CONDITIONS
fIN = 15.5 MHz
MIN
–1
TYP†
±
0.6
Assured
±
2
14
–7
70
– 10
LSB
mV
%FSR
MAX
1.25
UNIT
LSB
power supply
PARAMETER
I(AVDD)
I(DVDD)
Analog supply current
Digital supply current
TEST CONDITIONS
V(VIN) = (VCM)
V(VIN) = (VCM)
V(VIN) = (VCM)
V(VIN) = (VCM)
MIN
TYP†
73
2
2
380
MAX
110
4
7
UNIT
mA
mA
mA
mW
I(DRVDD) Output driver supply current‡
PD
Power dissipation
† All typical values are at TA = 25°C.
‡ 15 pF load on digital outputs
reference
PARAMETER
VREFOUT –
VREFOUT+
VREFIN –
VREFIN+
V(VCM)
Negative reference output voltage
Positive reference output voltage
External reference supplied
External reference supplied
Common mode output voltage
TEST CONDITIONS
MIN
1.9
2.9
TYP†
2
3
2
3
AVDD/2
80
MAX
2.1
3.1
UNIT
V
V
V
V
V
µA
I(VCM)
Common mode output current
† All typical values are at TA = 25°C.
analog input
PARAMETER
RI
CI
VI
VID
Differential input resistance
Differential input capacitance
Analog input common mode range
Differential input voltage range
–3 dB
TEST CONDITIONS
MIN
TYP†
1
4
VCM
±
0.05
2
120
MAX
UNIT
kΩ
pF
V
Vp-p
MHz
BW Analog input bandwidth (large signal)
† All typical values are at TA = 25°C.
digital outputs
PARAMETER
VOH
VOL
High-level output voltage
Low-level output voltage
TEST CONDITIONS
IOH = – 50
µA
IOL = 50
µA
MIN
0.8DRVDD
0.2DRVDD
15
TYP†
MAX
UNIT
V
VDD
pF
CL
Output load capacitance
† All typical values are at TA = 25°C.
4
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