The documentation and process conversion
measures necessary to comply with this revision
shall be completed by 30 October 1999
INCH-POUND
MIL-PRF-19500/547B
30 July 1999
SUPERSEDING
MIL-S-19500/547A
20 January 1988
PERFORMANCE SPECIFICATION SHEET
SEMICONDUCTOR DEVICE, FIELD EFFECT TRANSISTOR, N-CHANNEL,
SILICON TYPES 2N6660 AND 2N6661
JAN, JANTX, JANTXV AND JANS
This specification is approved for use by all Depart-
ments and Agencies of the Department of Defense.
1. SCOPE
1.1 Scope. This specification covers the performance requirements for a N-channel, enhancement-mode, low-threshold logic level,
high frequency, high switching speed MOSFET, power transistor. Four levels of product assurance are provided for each encapsulated
device type as specified in MIL-PRF-19500.
1.2 Physical dimensions. See figure 1 (TO-205AD).
1.3 Maximum ratings. Unless otherwise specified, TA = +25°C.
Type
PT 1/
PT
TC = +25°C TA = +25°C
W
2N6660
2N6661
6.25
6.25
mW
725
725
VDS
VDGR
3/
V dc
60
90
V dc
60
90
V dc
±
20
±
20
VGS
ID1 2/
ID2 2/
TC = +25°C TC = +100°C
A dc
0.99
0.86
A dc
0.62
0.54
IS
IDM
TJ and
TSTG
°C
-65 to +150
A dc
-0.99
-0.86
A(pk)
3
3
1/ Derate linearly 0.05 W/°C for TC > +25°C
2/ Derate above TC = +25
°C
according to the formula
where P(rated) = 150 - (TC -25) (0.05) watts;
K = max r
DS(on)
at TJ =+150°C.
3/ R
GS
≤
1 M ohm.
I
D
=
P
(
rated
)
K
Beneficial comments (recommendations, additions, deletions) and any pertinent data which may be of use in improving this document
should be addressed to: Commander, Defense Supply Center Columbus, ATTN: DSCC-VAC, 3990 East Broad St., Columbus, OH
43216-5000, by using the addressed Standardization Document Improvement Proposal (DD Form 1426) appearing at the end of this
document or by letter.
AMSC N/A
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.
FSC 5961
MIL-PRF-19500/547B
1.4 Primary electrical characteristics at TC = +25°C.
Type
Min V(BR)DSS
VGS = 0 V
ID = 10
µA
dc
VGS(th)1
VDS
≥
VGS
ID = 1.0 mA dc
Max IDSS1
VGS = 0 V
Max rDS(on) 1/
VGS = 10 V dc
R
θ
JC
Max
VDS = 80 percent
of
rated VDS
V dc
V dc
Min Max
0.8
0.8
2.0
2.0
µA
dc
TJ = +25°C
at ID1
TJ = +150°C
at ID2
°C/W
Ohm
Ohm
2N6660
2N6661
1/ Pulsed (see 4.5.1).
60
90
1.0
1.0
3.0
4.0
6.33
8.44
20
20
2. APPLICABLE DOCUMENTS
2.1 General. The documents listed in this section are specified in sections 3 and 4 of this specification. This section does not include
documents cited in other sections of this specification or recommended for additional information or as examples. While every effort has
been made to ensure the completeness of this list, document users are cautioned that they must meet all specified requirements
documents cited in section 3 and 4 of this specification, whether or not they are listed.
2.1.1 Specifications, standards, and handbooks. The following specifications, standards, and handbooks form a part of this document
to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in the issue of the Department
of Defense Index of Specifications and Standards (DODISS) and supplement thereto, cited in the solicitation (see 6.2).
SPECIFICATION
DEPARTMENT OF DEFENSE
MIL-PRF-19500
STANDARD
MILITARY
MIL-STD-750
- Test Methods for Semiconductor Devices.
- Semiconductor Devices, General Specification for.
(Unless otherwise indicated, copies of the above specifications, standards, and handbooks are available from the Defense Automated
Printing Service, Building 4D (DPM-DODSSP), 700 Robbins Avenue, Philadelphia, PA 19111-5094.)
2.2 Order of precedence. In the event of a conflict between the text of this specification and the references cited herein, the text of this
specification takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific
exemption has been obtained.
3. REQUIREMENTS
3.1 Associated specification. The individual item requirements shall be in accordance with MIL-PRF-19500 and as specified herein.
3.2 Abbreviations, symbols, and definitions. Abbreviations, symbols, and definitions used herein shall be as specified in MIL-PRF-
19500.
3.3 Interface requirements and physical dimensions. The Interface requirements and physical dimensions shall be as specified in
MIL-PRF-19500 and figure 1 (TO-205AD) herein.
2
MIL-PRF-19500/547B
FIGURE 1. Physical dimensions (TO-205AD).
3
MIL-PRF-19500/547B
Ltr
Inches
Min
CD
CH
HD
TW
TL
LD
LL
LC
LU
L1
L2
P
Q
R
α
0.250
0.100
0.305
0.240
0.335
0.028
0.029
0.016
0.500
Dimensions
Millimeters
Min
7.75
6.10
8.51
0.71
0.74
0.41
12.70
Max
8.51
6.60
9.40
0.86
1.14
0.53
19.05
Notes
Max
0.335
0.260
0.370
0.034
0.045
0.021
0.750
2
3
7,8
7,8
6
7,8
7,8
7,8
5
0.200 TP
0.016
0.019
0.050
5.08 TP
0.41
0.48
1.27
6.35
2.54
0.050
0.010
45 TP
1.27
0.25
45 TP
4
9
6
NOTES:
1. Dimensions are in inches. Metric equivalents are given for general information only.
2. Beyond radius (r) maximum, TW shall be held for a minimum length of 0.011 (0.028 mm).
3. Dimension TL measured from maximum HD.
4. Outline in this zone is not controlled.
5. Dimension CD shall not vary more than 0.010 (0.25 mm) in zone P. This zone is controlled for automatic handling.
6. Leads at gauge plane 0.054 + 0.001, - 0.000 (1.37 +0.03, -0.00 mm) below seating plane shall be within 0.007 (0.18 mm)
radius of true position (TP) at maximum material condition (MMC) relative to tab at MMC.
7. LU applies between L1 and L2. LD applies between L2 and L minimum. Diameter is uncontrolled in L1 and beyond LL
minimum.
8. All three leads.
9. Radius (r) applies to both inside corners of tab.
10.
Drain is electrically connected to the case.
FIGURE 1. Physical dimensions(TO-205AD) Continued.
4
MIL-PRF-19500/547B
3.3.1 Lead finish. Lead finish shall be solderable in accordance with MIL-PRF-19500, MIL-STD-750, and herein. Where a choice of
lead finish is desired, it shall be specified in the acquisition document (see 6.2).
3.3.2 Internal construction. Multiple chip construction shall not be permitted.
3.4 Marking. Marking shall be in accordance with MIL-PRF-19500.
3.5 Electrostatic discharge protection. The devices covered by this specification require electrostatic protection.
3.5.1 Handling. MOS devices must be handled with certain precautions to avoid damage due to the accumulation of static charge.
The following handling practices shall be followed:
a.
b.
c.
d.
e.
f.
g.
h.
Devices shall be handled on benches with conductive handling devices.
Ground test equipment, tools, and personnel handling devices.
Do not handle devices by the leads.
Store devices in conductive foam or carriers.
Avoid use of plastic, rubber, or silk in MOS areas.
Maintain relative humidity above 50 percent if practical.
Care shall be exercised, during test and troubleshooting, to apply not more than maximum rated voltage to any lead.
Gate must be terminated to source, R
≤
100 k, whenever bias voltage is to be applied drain to source.
3.6 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as
specified in 1.3, 1.4, and table I.
3.7 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table I herein.
3.8 Qualification. Devices furnished under this specification shall be products that are authorized by the qualifying activity for listing
on the applicable qualified manufacturer's list before contract award (see 4.2 and 6.3 ).
4. VERIFICATION
4.1 Classification of Inspections. The inspection requirements specified herein are classified as follows:
a. Qualification inspection (see 4.2).
b. Screening (see 4.3).
c. Conformance inspection (see 4.4).
4.2 Qualification inspection. Qualification inspection shall be in accordance with MIL-PRF-19500 and herein. Alternate flow is allowed
for qualification inspection in accordance with figure 4 of MIL-PRF-19500.
4.2.1 Group E inspection. Group E inspection shall be conducted in accordance with MIL-PRF-19500 and herein.
5
stm32/stm8
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