KAF-1001
1024 (H) x 1024 (V) Full
Frame CCD Image Sensor
Description
T h e K A F −1 0 0 1 I m a g e S e n s o r i s a h i g h - p e r f o r m a n c e
charge-coupled device (CCD) designed for a wide range of image
sensing applications.
The sensor incorporates true two-phase CCD technology,
simplifying the support circuits required to drive the sensor as well as
reducing dark current without compromising charge capacity.
The sensor also utilizes the TRUESENSE Transparent Gate Electrode
to improve sensitivity compared to the use of a standard front side
illuminated polysilicon electrode.
Selectable on-chip output amplifiers allow operation to be
optimized for different imaging needs: Low Noise (when using the
high-sensitivity output) or Maximum Dynamic Range (when using the
low-sensitivity output).
Table 1. GENERAL SPECIFICATIONS
Parameter
Architecture
Pixel Count
Pixel Size
Active Image Size
Typical Value
Full Frame CCD
1024 (H)
×
1024 (V)
24
mm
(H)
×
24
mm
(V)
24.6 mm (H)
×
24.6 mm (V)
34.8 mm (Diagonal)
APS−H Optical Format
28.6 mm (H)
×
25.5 mm (V)
100%
240,000 electrons
650,000 electrons
11
mV/electron
2
mV/electron
15 electrons rms
< 30 pA/cm
2
5−6°C
83 dB
97 dB
40%, 55%, 65%
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Figure 1. KAF−1001 CCD Image Sensor
Features
•
True Two Phase Full Frame Architecture
•
TRUESENSE Transparent Gate Electrode
•
•
•
•
for High Sensitivity
100% Fill Factor
Low Dark Current
Single Readout Register
User-selectable Outputs Allow either Low
Noise or High Dynamic Range Operation
Chip Size
Optical Fill-Factor
Saturation Signal
High Sensitivity Output
High Dynamic Range
Output Sensitivity
High Sensitivity Output
High Dynamic Range
Readout Noise (1 MHz)
Dark Current
(25°C, Accumulation Mode)
Dark Current Doubling Rate
Dynamic Range (Sat Sig/Dar Noise)
High Sensitivity Output
High Dynamic Range
Quantum Efficiency
(450, 550, 650 nm)
Maximum Data Rate
High Sensitivity Output
High Dynamic Range
Transfer Efficiency (2 MHz, to −40°C)
Package
Cover Glass
Applications
•
Scientific
•
Medical
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
5 MHz
2 MHz
> 0.99997
CERDIP Package (Sidebrazed)
Clear
NOTE: Parameters above are specified at T = 25°C unless otherwise noted.
©
Semiconductor Components Industries, LLC, 2015
1
December, 2015 − Rev. 2
Publication Order Number:
KAF−1001/D
KAF−1001
ORDERING INFORMATION
Table 2. ORDERING INFORMATION − KAF−1001 IMAGE SENSOR
Part Number
KAF−1001−AAA−CP−B1
KAF−1001−AAA−CP−B2
KAF−1001−AAA−CP−AE
KAF−1001−AAA−CB−AE
KAF−1001−AAA−CB−B2
Description
Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass (No Coatings), Grade 1
Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass (No Coatings), Grade 2
Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass (No Coatings), Engineering Sample
Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass (No Coatings), Engineering Sample
Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass (No Coatings), Grade 2
KAF−1001−AAA
Serial Number
Marking Code
Table 3. ORDERING INFORMATION − EVALUATION SUPPORT
Part Number
KEK−4H0080−KAF−1001−12−5
Evaluation Board (Complete Kit)
Description
See the ON Semiconductor
Device Nomenclature
document (TND310/D) for a full description of the naming convention
used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
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2
KAF−1001
DEVICE DESCRIPTION
Architecture
4 Dark Lines
KAF−1001
Usable Active Image Area
1024 (H)
×
1024 (V)
24
×
24
mm
Pixels
fV1
fV2
Guard
fH22
SUB
V
DD2
V
OUT2
V
SS
1024 Active Pixels/Line
4 Dark
4 Inactive
8 Dark
2 Inactive
FD1
FD2
4 Dark Lines
fH1
fH2
V
DD1
V
OUT1
fR
V
RD
V
OG
fH21
NOTE: Shaded areas represent 4 non-imaging pixels at the beginning and 8 non-imaging pixels at the end of each line. There are also
4 non-imaging lines at the top and bottom of each frame.
Figure 2. Block Diagram
Refer to the block diagram in Figure 2. The KAF−1001
consists of one vertical (parallel) CCD shift register, one
horizontal (serial) CCD shift register and a selectable high
or low gain output amplifier. Both registers incorporate true
two-phase buried channel technology. The vertical register
consists of 24
mm
×
24
mm
photo-capacitor sensing elements
(pixels) which also serves as the transport mechanism.
The pixels are arranged in a 1024 (H)
×
1024 (V) array;
an additional 12 columns (4 at the left and 8 at the right) and
8 rows (4 each at top and bottom) of non-imaging pixels are
added as dark reference. Because there is no storage array,
this device must be synchronized with strobe illumination or
shuttered during readout.
Output Structure
The final gate of the horizontal register is split into two
sections,
fH21
and
fH22.
The split gate structure allows the
user to select either of the two output amplifiers. To use the
high dynamic range single-stage output (V
OUT1
), tie
fH22
to a negative voltage to block charge transfer, and tie
fH21
to
fH2
to transfer charge. To use the high sensitivity
two-stage output (V
OUT2
), tie
fH21
to a negative voltage
and
fH22
to
fH2.
The charge packets are then dumped onto
the appropriate floating diffusion output node whose
potential varies linearly with the quantity of charge in each
packet. The amount of potential change is determined by the
simple expression
DV
fd
=
DQ/C
fd
. The translation from
electrons to voltages is called the output sensitivity or
charge-to-voltage conversion. After the output has been
sensed off-chip, the reset clock (fR) removes the charge
from the floating diffusion via the reset drain (VRD). This,
in turn, returns the floating diffusion potential to the
reference level determined by the reset drain voltage.
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É
É
KAF−1001
H2
H1
H2
H1L
V
OG
R
V
RD
Floating
Diffusion
V
OUT
HCCD
Charge
Transfer
V
DD
V
LG
Source
Follower
#1
Source
Follower
#2
Figure 3. Output Schematic
Image Acquisition
An image is acquired when incident light, in the form of
photons, falls on the array of pixels in the vertical CCD
register and creates electron-hole pairs (or simply electrons)
within the silicon substrate. This charge is collected locally
by the formation of potential wells created at each pixel site
by induced voltages on the vertical register clock lines
(fV1,
fV2).
These same clock lines are used to implement
the transport mechanism as well. The amount of charge
collected at each pixel is linearly dependent on light level
and exposure time and non-linearly dependent on
wavelength until the potential well capacity is exceeded. At
this point charge will ‘bloom’ into vertically adjacent pixels.
Charge Transport
Integrated charge is transported to the output in a two-step
process. Rows of charge are first shifted line by line into the
horizontal CCD. ‘Lines’ of charge are then shifted to the
output pixel by pixel. Referring to the timing diagram,
integration of charge is performed with
fV1
and
fV2
held
low. Transfer to horizontal CCD begins when
fV1
is
brought high causing charge from the
fV1
and
fV2
gates
to combine under the
fV1
gate.
fV1
and
fV2
now reverse their polarity causing the
charge packets to ‘spill’ forward under the
fV2
gate of the
next pixel. The rising edge of
fV2
also transfers the first line
of charge into the horizontal CCD. A second phase transition
places the charge packets under the
fV1
electrode of the
next pixel. The sequence completes when
fV1
is brought
low. Clocking of the vertical register in this way is known as
accumulation mode clocking. Next, the horizontal CCD
reads out the first line of charge using traditional
complementary clocking (using
fH1
and
fH2
pins) as
shown. The falling edge of
fH2
forces a charge packet over
the output gate (OG) onto one of the output nodes (floating
diffusion) which controls the output amplifier. The cycle
repeats until all lines are read.
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KAF−1001
Physical Description
Pin Description and Device Orientation
SUB 1
fV2
2
fV1
3
SUB 4
VOUT2 5
VDD2 6
VLG 7
VSS 8
fR
VRD
9
10
Pixel (1024, 1024)
26 SUB
25
fV2
24
fV1
23 GUARD
22
fV1
21
fV2
20 N/C
19 N/C
18 N/C
17
fH2
16
fH1
15
fH22
Pixel (1, 1)
14
fH21
VDD1 11
VOUT1 12
VOG
13
Figure 4. Pinout Diagram
Table 4. PIN DESCRIPTION
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
Name
SUB
fV2
fV1
SUB
VOUT2
VDD2
VLG
VSS
fR
VRD
VDD1
VOUT1
VOG
Substrate
Vertical (Parallel) CCD Clock − Phase 2
Vertical (Parallel) CCD Clock − Phase 1
Substrate
Video Output from High Sensitivity
Two-Stage Amplifier
High Sensitivity Two-Stage Amplifier
Supply
First Stage Load Transistor Gate for
Two-Stage Amplifier
Output Amplifier Return
Reset Clock
Reset Drain
High Dynamic Range Single-Stage
Amplifier Supply
Video Output from High Dynamic Range
Single-Stage Amplifier
Output Gate
15
16
17
18
19
20
21
22
23
24
25
26
fH22
fH1
fH2
N/C
N/C
N/C
fV2
fV1
GUARD
fV1
fV2
SUB
Last Horizontal (Serial) CCD Phase − Split
Gate
Horizontal (Serial) CCD Clock − Phase 1
Horizontal (Serial) CCD Clock − Phase 2
No Connection
No Connection
No Connection
Vertical (Parallel) CCD Clock − Phase 2
Vertical (Parallel) CCD Clock − Phase 1
Guard Ring
Vertical (Parallel) CCD Clock − Phase 1
Vertical (Parallel) CCD Clock − Phase 2
Substrate
Description
Pin
14
Name
fH21
Description
Last Horizontal (Serial) CCD Phase − Split
Gate
1. Pins 3, 22, and 24 must be connected together − only one
Phase 1 clock driver is required.
2. Pins 2, 21, and 25 must be connected together − only one
Phase 2 clock driver is required.
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