CAT25C64
64K-Bit SPI Serial CMOS EEPROM
FEATURES
I
10 MHz SPI compatible
I
1.8 to 5.5 volt operation
I
Hardware and software protection
I
Low power CMOS technology
I
SPI modes (0,0 &1,1)
I
Commercial, industrial and automotive
DESCRIPTION
The CAT25C64 is a 64K-Bit SPI Serial CMOS EEPROM
internally organized as 8Kx8 bits. Catalyst’s advanced
CMOS Technology substantially reduces device power
requirements. The CAT25C64 features a 64-byte page
write buffer. The device operates via the SPI bus serial
interface and is enabled though a Chip Select (CS). In
addition to the Chip Select, the clock input (SCK), data
in (SI) and data out (SO) are required to access the
device. The
HOLD
pin may be used to suspend any
serial communication without resetting the serial se-
quence. The CAT25C64 is designed with software and
hardware write protection features including Block write
protection. The device is available in 8-pin DIP and
SOIC packages.
temperature ranges
I
1,000,000 program/erase cycles
I
100 year data tetention
I
Self-timed write cycle
I
8-pin DIP and SOIC
I
64-Byte page write buffer
I
Block write protection
– Protect 1/4, 1/2 or all of EEPROM array
PIN CONFIGURATION
PDIP (P, L)
SOIC (S, V)
CS
SO
WP
VSS
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
FUNCTIONAL SYMBOL
VCC
SI
CS
WP
HOLD
SCK
CAT25C64
SO
PIN FUNCTIONS
Pin Name
SO
SCK
WP
V
CC
V
SS
CS
SI
HOLD
Function
Serial Data Output
Serial Clock
Write Protect
+1.8V to +5.5V Power Supply
Ground
Chip Select
Serial Data Input
Suspends Serial Input
VSS
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1112, Rev. B
CAT25C64
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to V
SS(1)
.................. –2.0V to +V
CC
+2.0V
V
CC
with Respect to V
SS ................................
–2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(2)
........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
N
END(3)
T
DR(3)
Parameter
Endurance
Data Retention
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
Min.
1,000,000
100
Max.
Units
Cycles/Byte
Years
D.C. OPERATING CHARACTERISTICS
V
CC
= +1.8V to +5.5V, unless otherwise specified.
Limits
Symbol
I
CC1
I
CC2
I
SB(4)
I
LI
I
LO
V
IL(5)
V
IH(5)
V
OL1
V
OH1
V
OL2
V
OH2
Parameter
Power Supply Current
(Operating Write)
Power Supply Current
(Operating Read)
Power Supply Current
(Standby)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
V
CC
-0.2
V
CC
- 0.8
0.2
-1
V
CC
x 0.7
Min.
Typ.
Max.
10
2
1
2
3
V
CC
x 0.3
V
CC
+ 0.5
0.4
2.7V
≤
V
CC
< 5.5V
I
OL
= 3.0mA
I
OH
= -1.6mA
1.8V
≤
V
CC
< 2.7V
I
OL
= 150µA
I
OH
= -100µA
V
OUT
= 0V to V
CC
,
CS = 0V
Test Conditions
V
CC
= 5V @ 10MHz
SO = open; CS = Vss
V
CC
= 5.0V
F
CLK
= 10MHz
CS
= V
CC
V
IN
= V
SS
or V
CC
Units
mA
mA
µA
µA
µA
V
V
V
V
V
V
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) These parameter are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Maximum standby current (ISB ) = 10µA for the Automotive and Extended Automotive temperature range.
(5) V
IL
min and V
IH
max are reference values only and are not tested.
Doc. No. 1112, Rev. B
2
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT25C64
PIN CAPACITANCE
(1)
Applicable over recommended operating range from T
A
=25˚C, f=1.0 MHz, VCC=+5.0V (unless otherwise noted).
Symbol
C
OUT
C
IN
Test Conditions
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI,
WP, HOLD)
Max.
8
6
Conditions
V
OUT
=0V
V
IN
=0V
Units
pF
pF
A.C. CHARACTERISTICS
CAT25C64-1.8
V
CC
=
1.8V - 5.5V
SYMBOL PARAMETER
t
SU
t
H
t
WH
t
WL
f
SCK
t
LZ
t
RI(1)
t
FI(1)
t
HD
t
CD
t
WC(3)
t
V
t
HO
t
DIS
t
HZ
t
CS
t
CSS
t
CSH
Data Setup Time
Data Hold Time
SCK High Time
SCK Low Time
Clock Frequency
HOLD
to Output Low Z
Input Rise Time
Input Fall Time
HOLD
Setup Time
HOLD
Hold Time
Write Cycle Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD
to Output High Z
CS
High Time
CS
Setup Time
CS
Hold Time
500
500
500
0
250
150
250
250
250
100
100
10
250
0
250
100
100
100
100
Min.
50
50
250
250
DC
1
50
2
2
100
100
10
125
0
75
50
Max.
CAT25C64
V
CC
=
2.5V - 5.5V
Min.
50
50
125
125
DC
3
50
2
2
40
40
5
40
C
L
= 50pF
(2)
Max.
V
CC
=
4.5V - 5.5V
Min.
20
20
40
40
DC
10
50
2
2
Max.
Test
Conditions UNITS
ns
ns
ns
ns
MHz
ns
µs
µs
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
Power-Up Timing
(4)(5)
Symbol
t
PUR
t
PUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
Max.
1
1
Units
ms
ms
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) AC Test Conditions:
Input Pulse Voltages: 0.3V
CC
to 0.7V
CC
Input rise and fall times:
≤10ns
Input and output reference voltages: 0.5V
CC
Output load: current source IOL max/IOH max; C
L
=50pF
(3) t
WC
is the time from the rising edge of
CS
after a valid write sequence to the end of the internal write cycle.
(4) This parameter is tested initially and after a design or process change that affects the parameter.
(5) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. 1112, Rev. B
CAT25C64
FUNCTIONAL DESCRIPTION
The CAT25C64 supports the SPI bus data transmission
protocol. The synchronous Serial Peripheral Interface
(SPI) helps the CAT25C64 to interface directly with
many of today’s popular microcontrollers. The CAT25C64
contains an 8-bit instruction register. (The instruction
set and the operation codes are detailed in the instruction
set table)
After the device is selected with
CS
going low, the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK.
The first byte contains one of the six op-codes that define
the operation to be performed.
Figure 1. Sychronous Data Timing
V
IH
PIN DESCRIPTION
SI: Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses, and data to be written to the
25C64. Input data is latched on the rising edge of the
serial clock.
SO: Serial Output
SO is the serial data output pin. This pin is used to
transfer data out of the 25C64. During a read cycle, data
is shifted out on the falling edge of the serial clock.
SCK: Serial Clock
SCK is the serial clock pin. This pin is used to synchronize
t
CS
CS
V
IL
V
IH
t
CSS
t
CSH
SCK
V
IL
t
SU
V
IH
t
WH
t
H
t
WL
SI
VIL
VALID IN
t
RI
tFI
t
V
V
OH
t
HO
t
DIS
HI-Z
SO
V
OL
HI-Z
Note: Dashed Line= mode (1, 1) — — — —
INSTRUCTION SET
Instruction
WREN
WRDI
RDSR
WRSR
READ
WRITE
Opcode
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Operation
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
Doc. No. 1112, Rev. B
4
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT25C64
the communication between the microcontroller and the
25C64. Opcodes, byte addresses, or data present on
the SI pin are latched on the rising edge of the SCK. Data
on the SO pin is updated on the falling edge of the SCK.
CS:
CS
Chip Select
CS
is the Chip select pin.
CS
low enables the CAT25C64
and
CS
high disables the CAT25C64.
CS
high takes the
SO output pin to high impedance and forces the devices
into a Standby Mode (unless an internal write operation
is underway). The CAT25C64 draws ZERO current in
the Standby mode. A high to low transition on
CS
is
required prior to any sequence being initiated. A low to
high transition on
CS
after a valid write sequence is what
initiates an internal write cycle.
WP:
WP
Write Protect
WP
is the Write Protect pin. The Write Protect pin will
allow normal read/write operations when held high.
When
WP
is tied low and the WPEN bit in the status
register is set to “1”, all write operations to the status
register are inhibited.
WP
going low while
CS
is still low
will interrupt a write to the status register. If the internal
write cycle has already been initiated,
WP
going low will
have no effect on any write operation to the status
register. The
WP
pin function is blocked when the WPEN
bit is set to 0.
HOLD:
HOLD
Hold
The
HOLD
pin is used to pause transmission to the
CAT25C64 while in the middle of a serial sequence
without having to re-transmit entire sequence at a later
time. To pause,
HOLD
must be brought low while SCK
is low. The SO pin is in a high impedance state during the
time the part is paused, and transitions on the SI pins will
be ignored. To resume communication,
HOLD
is brought
high, while SCK is low.
(HOLD
should be held high any
time this function is not being used.)
HOLD
may be tied
high directly to V
cc
or tied to V
cc
through a resistor.
Figure 9 illustrates hold timing sequence.
STATUS REGISTER
7
WPEN
6
X
5
X
4
X
3
BP1
2
BP0
1
WEL
0
RDY
BLOCK PROTECTION BITS
Status Register Bits
BP1
BP0
0
0
1
1
0
1
0
1
Array Address
Protected
None
1800-1FFF
1000-1FFF
0000-1FFF
Protection
No Protection
Quarter Array Protection
Half Array Protection
Full Array Protection
WRITE PROTECT ENABLE OPERATION
Protected
Blocks
Protected
Protected
Protected
Protected
Protected
Protected
Unprotected
Blocks
Protected
Writable
Protected
Writable
Protected
Writable
Status
Register
Protected
Writable
Protected
Protected
Protected
Writable
WPEN
0
0
1
1
X
X
WP
X
X
Low
Low
High
High
WEL
0
1
0
1
0
1
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. 1112, Rev. B
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