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CD4075BDMSR

产品描述4000/14000/40000 SERIES, TRIPLE 3-INPUT OR GATE, CDIP14, BRAZE SEALED, DIP-14
产品类别逻辑    逻辑   
文件大小116KB,共10页
制造商Renesas(瑞萨电子)
官网地址https://www.renesas.com/
下载文档 详细参数 选型对比 全文预览

CD4075BDMSR概述

4000/14000/40000 SERIES, TRIPLE 3-INPUT OR GATE, CDIP14, BRAZE SEALED, DIP-14

CD4075BDMSR规格参数

参数名称属性值
是否Rohs认证不符合
厂商名称Renesas(瑞萨电子)
零件包装代码DIP
包装说明DIP, DIP14,.3
针数14
Reach Compliance Codenot_compliant
系列4000/14000/40000
JESD-30 代码R-CDIP-T14
JESD-609代码e0
长度9.585 mm
负载电容(CL)50 pF
逻辑集成电路类型OR GATE
最大I(ol)0.00036 A
功能数量3
输入次数3
端子数量14
最高工作温度125 °C
最低工作温度-55 °C
封装主体材料CERAMIC, METAL-SEALED COFIRED
封装代码DIP
封装等效代码DIP14,.3
封装形状RECTANGULAR
封装形式IN-LINE
峰值回流温度(摄氏度)NOT SPECIFIED
电源5/15 V
Prop。Delay @ Nom-Sup338 ns
传播延迟(tpd)338 ns
认证状态Not Qualified
施密特触发器NO
筛选级别MIL-PRF-38535 Class V
座面最大高度5.33 mm
标称供电电压 (Vsup)5 V
表面贴装NO
技术CMOS
温度等级MILITARY
端子面层Tin/Lead (Sn/Pb)
端子形式THROUGH-HOLE
端子节距2.54 mm
端子位置DUAL
处于峰值回流温度下的最长时间NOT SPECIFIED
总剂量100k Rad(Si) V
宽度7.62 mm

文档预览

下载PDF文档
CD4071BMS, CD4072BMS
CD4075BMS
December 1992
CMOS OR Gate
Pinout
CD4071BMS
TOP VIEW
Features
• High-Voltage Types (20V Rating)
• CD4071BMS Quad 2-Input OR Gate
• CD4072BMS Dual 4-Input OR Gate
• CD4075BMS Triple 3-Input OR Gate
• Medium Speed Operation:
- tPHL, tPLH = 60ns (typ) at 10V
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25
o
C
• Standardized Symmetrical Output Characteristics
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
A 1
B 2
J=A+B 3
K=C+C 4
C 5
D 6
VSS 7
14 VDD
13 H
12 G
11 M = G + H
10 L = E + F
9 F
8 E
CD4072BMS
TOP VIEW
J=A+B+C+D 1
A 2
B 3
C 4
14 VDD
13 K = E +F + G + H
12 H
11 G
10 F
9 E
8 NC
Description
CD4071BMS, CD4072BMS and CD4075BMS OR gates pro-
vide the system designer with direct implementation of the
positive-logic OR function and supplement the existing fam-
ily of CMOS gates.
The CD4071BMS, CD4072BMS and CD4075BMS are supplied
in these 14 lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
*CD4071, CD4072
*H4H
H1B
H3W
†CD4075 Only
†H4Q
D 5
NC 6
VSS 7
NC = NO CONNECTION
CD4075BMS
TOP VIEW
A 1
B 2
D 3
E 4
F 5
K=D+E+F 6
VSS 7
14 VDD
13 G
12 H
11 I
10 L = G + H + I
9 J=A+B+C
8 C
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
File Number
3323
7-444

CD4075BDMSR相似产品对比

CD4075BDMSR CD4072BDMSR CD4072BFMSR CD4075BFMSR CD4072BKMSR CD4071BFMSR CD4075BKMSR
描述 4000/14000/40000 SERIES, TRIPLE 3-INPUT OR GATE, CDIP14, BRAZE SEALED, DIP-14 4000/14000/40000 SERIES, DUAL 4-INPUT OR GATE, CDIP14, BRAZE SEALED, DIP-14 4000/14000/40000 SERIES, DUAL 4-INPUT OR GATE, CDIP14, FRIT SEALED, DIP-14 4000/14000/40000 SERIES, TRIPLE 3-INPUT OR GATE, CDIP14 4000/14000/40000 SERIES, DUAL 4-INPUT OR GATE, CDFP14 4000/14000/40000 SERIES, QUAD 2-INPUT OR GATE, CDIP14, FRIT SEALED, DIP-14 4000/14000/40000 SERIES, TRIPLE 3-INPUT OR GATE, CDFP14, CERAMIC, DFP-14
零件包装代码 DIP DIP DIP DIP DFP DIP DFP
包装说明 DIP, DIP14,.3 BRAZE SEALED, DIP-14 FRIT SEALED, DIP-14 DIP, DIP14,.3 DFP, FL14,.3 DIP, DIP14,.3 DFP, FL14,.3
针数 14 14 14 14 14 14 14
Reach Compliance Code not_compliant not_compliant not_compliant not_compliant not_compliant unknown not_compliant
系列 4000/14000/40000 4000/14000/40000 4000/14000/40000 4000/14000/40000 4000/14000/40000 4000/14000/40000 4000/14000/40000
JESD-30 代码 R-CDIP-T14 R-CDIP-T14 R-GDIP-T14 R-GDIP-T14 R-CDFP-F14 R-GDIP-T14 R-CDFP-F14
长度 9.585 mm 9.585 mm 9.585 mm 9.585 mm 9.585 mm 9.585 mm 9.585 mm
负载电容(CL) 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF
逻辑集成电路类型 OR GATE OR GATE OR GATE OR GATE OR GATE OR GATE OR GATE
最大I(ol) 0.00036 A 0.00036 A 0.00036 A 0.00036 A 0.00036 A 0.00036 A 0.00036 A
功能数量 3 2 2 3 2 4 3
输入次数 3 4 4 3 4 2 3
端子数量 14 14 14 14 14 14 14
最高工作温度 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C
最低工作温度 -55 °C -55 °C -55 °C -55 °C -55 °C -55 °C -55 °C
封装主体材料 CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED CERAMIC, GLASS-SEALED CERAMIC, GLASS-SEALED CERAMIC, METAL-SEALED COFIRED CERAMIC, GLASS-SEALED CERAMIC, METAL-SEALED COFIRED
封装代码 DIP DIP DIP DIP DFP DIP DFP
封装等效代码 DIP14,.3 DIP14,.3 DIP14,.3 DIP14,.3 FL14,.3 DIP14,.3 FL14,.3
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 IN-LINE IN-LINE IN-LINE IN-LINE FLATPACK IN-LINE FLATPACK
电源 5/15 V 5/15 V 5/15 V 5/15 V 5/15 V 5/15 V 5/15 V
Prop。Delay @ Nom-Sup 338 ns 338 ns 338 ns 338 ns 338 ns 338 ns 338 ns
传播延迟(tpd) 338 ns 338 ns 338 ns 338 ns 338 ns 338 ns 338 ns
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
施密特触发器 NO NO NO NO NO NO NO
筛选级别 MIL-PRF-38535 Class V MIL-PRF-38535 Class V MIL-PRF-38535 Class V MIL-PRF-38535 Class V MIL-PRF-38535 Class V MIL-PRF-38535 Class V MIL-PRF-38535 Class V
座面最大高度 5.33 mm 5.33 mm 5.33 mm 5.33 mm 5.33 mm 5.33 mm 5.33 mm
标称供电电压 (Vsup) 5 V 5 V 5 V 5 V 5 V 5 V 5 V
表面贴装 NO NO NO NO YES NO YES
技术 CMOS CMOS CMOS CMOS CMOS CMOS CMOS
温度等级 MILITARY MILITARY MILITARY MILITARY MILITARY MILITARY MILITARY
端子形式 THROUGH-HOLE THROUGH-HOLE THROUGH-HOLE THROUGH-HOLE FLAT THROUGH-HOLE FLAT
端子节距 2.54 mm 2.54 mm 2.54 mm 2.54 mm 1.27 mm 2.54 mm 1.27 mm
端子位置 DUAL DUAL DUAL DUAL DUAL DUAL DUAL
总剂量 100k Rad(Si) V 100k Rad(Si) V 100k Rad(Si) V 100k Rad(Si) V 100k Rad(Si) V 100k Rad(Si) V 100k Rad(Si) V
宽度 7.62 mm 7.62 mm 7.62 mm 7.62 mm 6.285 mm 7.62 mm 6.285 mm
是否Rohs认证 不符合 不符合 不符合 不符合 不符合 - 不符合
厂商名称 Renesas(瑞萨电子) Renesas(瑞萨电子) Renesas(瑞萨电子) - Renesas(瑞萨电子) Renesas(瑞萨电子) Renesas(瑞萨电子)
JESD-609代码 e0 e0 e0 e0 e0 - e0
峰值回流温度(摄氏度) NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED - NOT SPECIFIED
端子面层 Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) - Tin/Lead (Sn/Pb)
处于峰值回流温度下的最长时间 NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED - NOT SPECIFIED

 
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