K4R271669F
Direct RDRAM
™
128Mbit RDRAM (F-die)
256K x 16 bit x 32s Banks
Direct RDRAM
TM
Version 1.41
January 2004
Page -1
Version 1.41 Jan. 2004
K4R271669F
Change History
Version 1.4 ( September 2003 )
Direct RDRAM
™
- First Copy
( Version 1.4 is named to unify the version of component and device operation datasheets)
- Based on the 128Mbit E-die RDRAM
for short channel Datasheet Version 1.4
Version 1.41 ( January 2004 )
- Add the part number for leaded package.
Page 0
Version 1.41 Jan. 2004
K4R271669F
Overview
The RDRAM
device is a general purpose high-perfor-
mance memory device suitable for use in a broad range of
applications including communications, graphics, video and
any other application where high bandwidth and low latency
are required.
The 128Mbit RDRAM devices are extremely high-speed
CMOS DRAMs organized as 8M words by 16. The use of
Rambus Signaling Level (RSL) technology permits 800MHz
transfer rates while using conventional system and board
design technologies.
RDRAM devices are capable of sustained data transfers at
1.25 ns per two bytes (10ns per sixteen bytes).
The architecture of RDRAM devices allows the highest
sustained bandwidth for multiple, simultaneous randomly
addressed memory transactions. The separate control and
data buses with independent row and column control yield
over 95% bus efficiency. The RDRAM device's 32 banks
support up to four simultaneous transactions.
System oriented features for mobile, graphics and communi-
cations include power management and byte masking.
Direct RDRAM
™
SEC 240
x
CS8
K4R271669F
Figure 1: Direct RDRAM CSP Package
The 128Mbit RDRAM devices are offered in a horizontal
center-bond fanout CSP package.
Key Timing Parameters/Part Numbers
Speed
Organization
t
RAC
I/O
(Row
Bin Freq.
Access
MHz
Time) ns
-CS8
-CS8
800
800
45
45
Features
♦
Highest sustained bandwidth per DRAM device
-
1.6GB/s
sustained data transfer rate
- Separate control and data buses for maximized
efficiency
- Separate row and column control buses for
easy scheduling and highest performance
- 32 banks: four transactions can take place simul-
taneously at full bandwidth data rates
♦
Low latency features
Part Number
256Kx16x32s
a
256Kx16x32s
K4R271669F-T
b
CS8
K4R271669F-R
c
CS8
- Write buffer to reduce read latency
- 3 precharge mechanisms for controller flexibility
- Interleaved transactions
♦
Advanced power management:
a.
“32s”
- 32 banks which use a
“split”
bank architecture.
b.
“T”
- Lead free consumer package.
c.
“R”
- Leaded consumer package.
- Multiple low power states allows flexibility in power
consumption versus time to transition to active state
- Power-down self-refresh
♦
Organization: 1Kbyte pages and 32 banks
♦
Uses Rambus Signaling Level (RSL) interface
for up
to 800MHz operation
♦
WBGA package(54 Balls)
Page 1
Version 1.41 Jan. 2004
K4R271669F
Pinouts and Definitions
The following table shows the pin assignments of the center-
bonded RDRAM package.
Table 1: Center-Bonded CSP Device (Top View)
7
6
5
4
3
2
1
Top View
SCK
VCMOS
NC
GND
DQA6
DQA3
VDD
DQA1
DQA0
GND
VREF
CTMN
GND
RQ7
CTM
VDD
RQ1
RQ4
DQA7
GND
CMD
DQA4
DQA5
VDD
CFM
DQA2
GND
CFMN
VDDA
GNDA
RQ5
RQ6
VDD
RQ3
RQ2
GND
Direct RDRAM
™
DQB0
DQB1
VDD
DQB4
DQB5
VDD
DQB7
GND
SIO0
GND
DQB2
RQ0
GND
DQB6
DQB3
SIO1
VCMOS
NC
A
B
C
D
E
F
G
H
J
b. Top marking example
SEC 240
x
CS8
K4R271669F
Top View
Chip
For consumer package, pin #1(ROW 1, COL A) is
located at the A1 position on the top side and the A1
position is marked by the marker
“
•
“
.
Page 2
Version 1.41 Jan. 2004
K4R271669F
Direct RDRAM
™
Table 2: Pin Description
Signal
I/O
Type
CMOS
a
# Pins
center
2
Description
Serial input/output. Pins for reading from and writing to the control regis-
ters using a serial access protocol. Also used for power management.
Command input. Pins used in conjunction with SIO0 and SIO1 for reading
from and writing to the control registers. Also used for power manage-
ment.
Serial clock input. Clock source used for reading from and writing to the
control registers
Supply voltage for the RDRAM core and interface logic.
Supply voltage for the RDRAM analog circuitry.
Supply voltage for CMOS input/output pins.
Ground reference for RDRAM core and interface.
Ground reference for RDRAM analog circuitry.
Data byte A. Eight pins which carry a byte of read or write data between
the Channel and the RDRAM device.
Clock from master. Interface clock used for receiving RSL signals from
the Channel. Positive polarity.
Clock from master. Interface clock used for receiving RSL signals from
the Channel. Negative polarity
Logic threshold reference voltage for RSL signals
Clock to master. Interface clock used for transmitting RSL signals to the
Channel. Negative polarity.
Clock to master. Interface clock used for transmitting RSL signals to the
Channel. Positive polarity.
Row access control. Three pins containing control and address informa-
tion for row accesses.
Column access control. Five pins containing control and address informa-
tion for column accesses.
Data byte B.Eight pins which carry a byte of read or write data between
the Channel and the RDRAM device.
No Connection.
SIO1,SIO0
I/O
CMD
I
CMOS
a
1
SCK
V
DD
V
DDa
V
CMOS
GND
GNDa
DQA7..DQA0
CFM
CFMN
V
REF
CTMN
CTM
RQ7..RQ5 or
ROW2..ROW0
RQ4..RQ0 or
COL4..COL0
DQB7..
DQB0
NC
I
CMOS
a
1
6
1
2
9
1
I/O
I
I
RSL
b
RSL
b
RSL
b
8
1
1
1
I
I
I
I
I/O
RSL
b
RSL
b
RSL
b
RSL
b
RSL
b
1
1
3
5
8
2
54
Total pin count per package
a. All CMOS signals are high-true; a high voltage is a logic one and a low voltage is logic zero.
b. All RSL signals are low-true; a low voltage is a logic one and a high voltage is logic zero.
Page 3
Version 1.41 Jan. 2004
FPGA/CPLD
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