74ACTQ273 Quiet Series Octal D-Type Flip-Flop
May 2007
74ACTQ273
Quiet Series Octal D-Type Flip-Flop
Features
■
I
CC
reduced by 50%
■
Guaranteed simultaneous switching noise level and
■
■
■
■
■
tm
General Description
The ACTQ273 has eight edge-triggered D-type flip-flops
with individual D inputs and Q outputs. The common
buffered Clock (CP) and Master Reset (MR) input load
and reset (clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each
D-type input, one setup time before the LOW-to-HIGH
clock transition, is transferred to the corresponding flip-
flop's Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output
only is required and the Clock and Master Reset are
common to all storage elements.
The ACTQ utilizes Fairchild Quiet Series™ technology to
guarantee quiet output switching and improved dynamic
threshold performance. FACT Quiet Series™ features
GTO™ output control and undershoot corrector in addi-
tion to a split ground bus for superior performance.
dynamic threshold performance
Guaranteed pin-to-pin skew AC performance
Improved latch-up immunity
Buffered common clock and asynchronous master
reset
Outputs source/sink 24mA
4kV minimum ESD immunity
Ordering Information
Order Number
74ACTQ273SC
74ACTQ273SJ
74ACTQ273MTC
Package
Number
M20B
M20D
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Connection Diagram
Pin Description
Pin Names
D
0
–D
7
MR
CP
Q
0
–Q
7
Description
Data Inputs
Master Reset
Clock Pulse Input
Data Outputs
FACT™, FACT Quiet Series™, and GTO™ are trademarks of Fairchild Semiconductor Corporation.
©1989 Fairchild Semiconductor Corporation
74ACTQ273 Rev. 1.4
www.fairchildsemi.com
74ACTQ273 Quiet Series Octal D-Type Flip-Flop
Logic Symbols
Mode Select-Function Table
Operating
Mode
Reset (Clear)
Load “1”
Load “0”
Inputs
MR
L
H
H
Outputs
D
n
X
H
L
CP
X
Q
n
L
H
L
IEEE/IEC
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
=
LOW-to-HIGH Transition
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
©1989 Fairchild Semiconductor Corporation
74ACTQ273 Rev. 1.4
www.fairchildsemi.com
2
74ACTQ273 Quiet Series Octal D-Type Flip-Flop
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
I
IK
Supply Voltage
DC Input Diode Current
V
I
=
–0.5V
V
I
=
V
CC
+ 0.5V
V
I
I
OK
DC Input Voltage
DC Output Diode Current
V
O
=
–0.5V
V
O
=
V
CC
+ 0.5V
V
O
I
O
DC Output Voltage
Parameter
Rating
–0.5V to +7.0V
–20mA
+20mA
–0.5V to V
CC
+ 0.5V
–20mA
+20mA
–0.5V to V
CC
+ 0.5V
±50mA
±50mA
–65°C to +150°C
±300mA
140°C
DC Output Source or Sink Current
I
CC
or I
GND
DC V
CC
or Ground Current per Output Pin
T
STG
Storage Temperature
DC Latch-Up Source or Sink Current
T
J
Junction Temperature
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
V
I
V
O
T
A
∆
V /
∆
t
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Minimum Input Edge Rate:
Parameter
Rating
4.5V to 5.5V
0V to V
CC
0V to V
CC
–40°C to +85°C
125mV/ns
V
IN
from 0.8V to 2.0V, V
CC
@ 4.5V, 5.5V
©1989 Fairchild Semiconductor Corporation
74ACTQ273 Rev. 1.4
www.fairchildsemi.com
3
74ACTQ273 Quiet Series Octal D-Type Flip-Flop
DC Electrical Characteristics
T
A
=
+25°C
Symbol
V
IH
V
IL
V
OH
T
A
=
–40°C to +85°C
Units
V
V
V
2.0
2.0
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
±1.0
1.5
75
–75
µA
mA
mA
mA
µA
V
V
V
V
V
Parameter
Minimum HIGH Level
Input Voltage
Maximum LOW Level
Input Voltage
Minimum HIGH Level
Output Voltage
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
Conditions
V
OUT
=
0.1V
or V
CC
– 0.1V
V
OUT
=
0.1V
or V
CC
– 0.1V
I
OUT
=
–50µA
V
IN
=
V
IL
or V
IH
:
Typ.
1.5
1.5
1.5
1.5
4.49
5.49
2.0
2.0
0.8
0.8
4.4
5.4
Guaranteed Limits
4.5
5.5
V
OL
Maximum LOW Level
Output Voltage
4.5
5.5
I
OH
=
–24mA
I
OH
=
–24mA
(1)
I
OUT
=
50µA
V
IN
=
V
IL
or V
IH
:
0.001
0.001
I
OL
=
24mA
I
OL
=
24mA
(1)
V
I
=
V
CC
, GND
V
I
=
V
CC
– 2.1V
V
OLD
=
1.65V Max.
V
OHD
=
3.85V Min.
V
IN
=
V
CC
or GND
Figures 1 & 2
(3)
Figures 1 & 2
(3)
(4)
3.86
4.86
0.1
0.1
0.36
0.36
±0.1
0.6
4.5
5.5
I
IN
I
CCT
I
OLD
I
OHD
I
CC
V
OLP
V
OLV
V
IHD
V
ILD
Maximum Input
Leakage Current
Maximum I
CC
/Input
Minimum Dynamic
Output Current
(2)
Maximum Quiescent
Supply Current
Quiet Output Maximum
Dynamic V
OL
Quiet Output Minimum
Dynamic V
OL
Minimum HIGH Level
Dynamic Input Voltage
Maximum LOW Level
Dynamic Input Voltage
5.5
5.5
5.5
5.5
5.5
5.0
5.0
5.0
5.0
4.0
1.1
–0.6
1.9
1.2
1.5
–1.2
2.2
0.8
40.0
(4)
Notes:
1. All outputs loaded; thresholds on input associated with output under test.
2. Maximum test duration 2.0ms, one output loaded at a time.
3. Max number of outputs defined as (n). n–1 Data inputs are driven 0V to 3V; one output @ GND.
4. Max number of Data Inputs (n) switching. (n–1) Inputs switching 0V to 3V (ACTQ). Input-under-test switching:
3V to threshold (V
ILD
), 0V to threshold (V
IHD
) f
=
1 MHz.
©1989 Fairchild Semiconductor Corporation
74ACTQ273 Rev. 1.4
www.fairchildsemi.com
4
74ACTQ273 Quiet Series Octal D-Type Flip-Flop
AC Electrical Characteristics
T
A
=
+25°C,
C
L
=
50pF
Symbol
f
MAX
t
PLH
, t
PHL
t
PHL
T
A
=
–40°C to +85°C,
C
L
=
50pF
Min.
110
8.5
9.0
1.0
1.5
1.5
9.0
9.5
1.0
Parameter
Maximum Clock
Frequency
Propagation Delay,
CP to Q
n
Propagation Delay,
MR to Q
n
V
CC
(V)
(5)
5.0
5.0
5.0
5.0
Min.
125
1.5
1.5
Typ.
189
6.5
7.0
0.5
Max.
Max.
Units
MHz
ns
ns
ns
t
OSHL
, t
OSLH
Output to Output Skew
(6)
Notes:
5. Voltage range 5.0 is 5.0V ± 0.5V.
6. Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs
within the same packaged device. The specification applies to any outputs switching in the same direction, either
HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
). Parameter guaranteed by design. Not tested.
AC Operating Requirements
T
A
=
+25°C,
C
L
=
50 pF
Symbol
t
S
t
H
t
W
t
W
t
W
T
A
=
–40°C to +85°C,
C
L
=
50pF
Units
ns
ns
ns
ns
ns
3.5
1.5
4.0
4.0
3.0
Parameter
Setup Time, HIGH or LOW, D
n
to CP
Hold Time, HIGH or LOW, D
n
to CP
Clock Pulse Width, HIGH or LOW
MR Pulse Width, HIGH or LOW
Recovery Time, MR to CP
V
CC
(V)
(7)
5.0
5.0
5.0
5.0
5.0
Typ.
1.0
–0.5
2.0
1.5
0.5
Guaranteed Minimum
3.5
1.5
4.0
4.0
3.0
Note:
7. Voltage range 5.0 is 5.0V ± 0.5V.
Capacitance
Symbol
C
IN
C
PD
Parameter
Input Capacitance
Power Dissipation Capacitance
Conditions
V
CC
=
OPEN
V
CC
=
5.0V
Typ.
4.5
40.0
Units
pF
pF
©1989 Fairchild Semiconductor Corporation
74ACTQ273 Rev. 1.4
www.fairchildsemi.com
5
实时操作系统RTOS
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
