CY8C28243/CY8C28403/CY8C28413
CY8C28433/CY8C28445/CY8C28452
CY8C28513/CY8C28545
CY8C28623/CY8C28643/CY8C28645
PSoC
®
Programmable System-on-Chip™
Features
■
■
Varied resource options within one PSoC
®
device group
Powerful Harvard-architecture processor
❐
M8C processor speeds up to 24 MHz
❐
8 × 8 Multiply, 32-bit accumulate
❐
Low power at high speed
❐
Operating voltage: 3.0 V to 5.25 V
❐
Operating voltages down to 1.5 V Using on-chip switched
mode pump (SMP)
❐
Industrial temperature range: –40 °C to +85 °C
Advanced reconfigurable peripherals (PSoC Blocks)
❐
Up to 12 rail-to-rail analog PSoC blocks provide:
• Up to 14-bit ADCs
• Up to 9-bit DACs
• Programmable gain amplifiers
• Programmable filters and comparators
• Multiple ADC configurations
• Dedicated SAR ADC, up to 142 ksps with sample and hold
• Up to 4 synchronized or independent delta-sigma ADCs for
advanced applications
❐
Up to 4 limited type E analog blocks provide:
• Dual channel capacitive sensing capability
• Comparators with programmable DAC reference
• Up to 10-bit single-slope ADCs
❐
Up to 12 digital PSoC blocks provide:
• 8- to 32-bit timers and counters, 8- and 16-bit pulse-width
modulators (PWMs)
• Shift register, CRC, and PRS modules
• Up to 3 full-duplex UARTs
• Up to 6 half-duplex UARTs
• Multiple variable data length SPI masters or slaves
• Connectable to all GPIOs
❐
Complex peripherals by combining blocks
Precision, programmable clocking
❐
Internal ±2.5% 24/48 MHz main oscillator
❐
Optional 32.768 kHz crystal for precise on-chip clocks
❐
Optional external oscillator, up to 24 MHz
❐
Internal low speed, low power oscillator for watchdog and
sleep functionality
Flexible on-chip memory
❐
16 KB flash program storage 50,000 erase/write cycles
❐
1-KB SRAM data storage
❐
In-system serial programming (ISSP)
❐
Partial flash updates
❐
Flexible protection modes
❐
EEPROM emulation in flash
Programmable Pin configurations
❐
25 mA sink, 10 mA drive on all GPIOs
Pull-up, pull-down, high Z, strong, or open-drain drive modes
on all GPIOs
❐
Analog input on all GPIOs
❐
30 mA analog outputs on GPIOs
❐
Configurable interrupt on all GPIOs
❐
■
■
Additional system resources
2
❐
Up to two hardware I C resources
• Each resource implements slave, master, or multi-master
modes
• Operation between 0 and 400 kHz
❐
Watchdog and Sleep timers
❐
User-configurable low voltage detection
❐
Flexible internal voltage references
❐
Integrated supervisory circuit
❐
On-chip precision voltage reference
Complete development tools
❐
Free development software (PSoC Designer™)
❐
Full featured in-circuit emulator, and programmer
❐
Full speed emulation
❐
Flexible and functional breakpoint structure
❐
128 KB trace memory
■
Logic Block Diagram
Port 5 Port 4 Port 3 Port 2 Port 1 Port 0
PSoC
CORE
System Bus
Global Digital Interconnect
SRAM
1K
Interrupt
Controller
SROM
Analog
Drivers
Global Analog Interconnect
Flash 16K
Sleep and
Watchdog
CPU Core (M8C)
■
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
Digital
Block
Array
ANALOG SYSTEM
Analog
Block
Array
Analog
Ref.
■
Analog
Input
Muxing
Digital
Clocks
2
MACs
4 Type 2
2 I
2
C
Decimators Blocks
POR and LVD
System Resets
■
Internal
Voltage
Ref.
Switch
Mode
Pump
SYSTEM RESOURCES
Cypress Semiconductor Corporation
Document Number: 001-48111 Rev. *P
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised May 2, 2017
CY8C28243/CY8C28403/CY8C28413
CY8C28433/CY8C28445/CY8C28452
CY8C28513/CY8C28545
CY8C28623/CY8C28643/CY8C28645
Contents
More Information .............................................................. 3
PSoC Designer .................................................................. 3
PSoC Functional Overview .............................................. 4
The PSoC Core ........................................................... 4
The Digital System ...................................................... 4
The Analog System ..................................................... 5
System Resources ...................................................... 8
PSoC Device Characteristics ...................................... 8
Development Tools ........................................................ 10
PSoC Designer Software Subsystems ...................... 10
Designing with PSoC Designer ..................................... 11
Select User Modules ................................................. 11
Configure User Modules ............................................ 11
Organize and Connect .............................................. 11
Generate, Verify, and Debug ..................................... 11
Pinouts ............................................................................ 12
20-pin Part Pinout ...................................................... 12
28-pin Part Pinout ...................................................... 13
44-pin Part Pinout ...................................................... 14
48-pin Part Pinout ...................................................... 15
56-pin Part Pinout ...................................................... 16
Register Reference ......................................................... 18
Register Conventions ................................................ 18
Register Mapping Tables .......................................... 18
Electrical Specifications ................................................ 33
Absolute Maximum Ratings ....................................... 34
Operating Temperature ............................................. 34
DC Electrical Characteristics ..................................... 35
AC Electrical Characteristics ..................................... 55
Packaging Information ................................................... 68
Packaging Dimensions .............................................. 68
Thermal Impedances ................................................. 72
Capacitance on Crystal Pins ..................................... 72
Solder Reflow Specifications ..................................... 72
Development Tool Selection ......................................... 73
Software .................................................................... 73
Development Kits ...................................................... 73
Evaluation Tools ........................................................ 73
Device Programmers ................................................. 74
Accessories (Emulation and Programming) .............. 74
Ordering Information ...................................................... 75
Ordering Code Definitions ......................................... 76
Acronyms ........................................................................ 77
Acronyms Used ......................................................... 77
Reference Documents .................................................... 77
Document Conventions ................................................. 78
Units of Measure ....................................................... 78
Numeric Conventions ................................................ 78
Glossary .......................................................................... 78
Errata ............................................................................... 83
Part Numbers Affected .............................................. 83
Qualification Status ................................................... 83
Errata Summary ........................................................ 83
Document History Page ................................................. 85
Sales, Solutions, and Legal Information ...................... 87
Worldwide Sales and Design Support ....................... 87
Products .................................................................... 87
PSoC® Solutions ...................................................... 87
Cypress Developer Community ................................. 87
Technical Support ..................................................... 87
Document Number: 001-48111 Rev. *P
Page 2 of 87
CY8C28243/CY8C28403/CY8C28413
CY8C28433/CY8C28445/CY8C28452
CY8C28513/CY8C28545
CY8C28623/CY8C28643/CY8C28645
More Information
Cypress provides a wealth of data at
www.cypress.com
to help
you to select the right PSoC device for your design, and to help
you to quickly and effectively integrate the device into your
design. For a comprehensive list of resources, see the
knowledge base article “How
to Design with PSoC
®
1,
PowerPSoC
®
, and PLC – KBA88292”.
Following is an
abbreviated list for PSoC 1:
■
■
■
■
Note:
For CY8C28xxx devices related Development Kits please
click
here.
The
MiniProg1
and
MiniProg3
devices provide interfaces for
flash programming and debug.
PSoC Designer
PSoC Designer
is a free Windows-based Integrated Design
Environment (IDE). Develop your applications using a library of
pre-characterized analog and digital peripherals in a
drag-and-drop design environment. Then, customize your
design leveraging the dynamically generated API libraries of
code.
Figure 1
shows PSoC Designer windows.
Note:
This is not
the default view.
1.
Global Resources –
all device hardware settings.
2.
Parameters –
the parameters of the currently selected User
Modules.
3.
Pinout –
information related to device pins.
4.
Chip-Level Editor –
a diagram of the resources available on
the selected chip.
5.
Datasheet –
the datasheet for the currently selected UM
6.
User Modules –
all available User Modules for the selected
device.
7.
Device Resource Meter –
device resource usage for the
current project configuration.
8.
Workspace –
a tree level diagram of files associated with the
project.
9.
Output –
output from project build and debug operations.
Note:
For detailed information on PSoC Designer, go to
PSoC
®
Designer > Help > Documentation >
Designer Specific Documents > IDE User Guide.
Overview: PSoC Portfolio, PSoC Roadmap
Product Selectors:
PSoC 1, PSoC 3, PSoC 4, PSoC 5LP
In addition, PSoC Designer includes a device selection tool.
Application notes: Cypress offers a large number of PSoC
application notes covering a broad range of topics, from basic
to advanced level. Recommended application notes for getting
started with PSoC 1 are:
®
❐
Getting Started with PSoC 1 – AN75320.
®
❐
PSoC 1 - Getting Started with GPIO – AN2094.
®
❐
PSoC 1 Analog Structure and Configuration – AN74170.
®
❐
PSoC 1 Switched Capacitor Analog Blocks – AN2041.
❐
Selecting Analog Ground and Reference – AN2219.
Note:
For CY8C28xxx devices related Application note please
click
here.
■
Development Kits:
❐
CY3210-PSoCEval1
supports all PSoC 1 Mixed-Signal Array
families, including automotive, except CY8C25/26xxx
devices. The kit includes an LCD module, potentiometer,
LEDs, and breadboarding space.
❐
CY3214-PSoCEvalUSB
features a development board for
the CY8C24x94 PSoC device. Special features of the board
include USB and CapSense development and debugging
support.
Figure 1. PSoC Designer Layout
Document Number: 001-48111 Rev. *P
Page 3 of 87
CY8C28243/CY8C28403/CY8C28413
CY8C28433/CY8C28445/CY8C28452
CY8C28513/CY8C28545
CY8C28623/CY8C28643/CY8C28645
PSoC Functional Overview
The PSoC family consists of many devices with On-Chip
Controllers. These devices are designed to replace multiple
traditional MCU based system components with one low cost
single chip programmable component. A PSoC device includes
configurable analog blocks, digital blocks, and interconnections.
This architecture enables the user to create customized
peripheral configurations to match the requirements of each
individual application. In addition, a fast CPU, Flash program
memory, SRAM data memory, and configurable I/O are included
in a range of convenient pinouts and packages.
The CY8C28xxx group of PSoC devices described in this
datasheet have multiple resource configuration options
available. Therefore, not every resource mentioned in this
datasheet is available for each CY8C28xxx subgroup. The
CY8C28x45 subgroup has a full feature set of all resources
described. There are six more segmented subgroups that allow
designers to use a device with only the resources and
functionality necessary for a specific application. See
Table 2
on
page 9 to determine the resources available for each
CY8C28xxx subgroup. The same information is also presented
in more detail in the
Ordering Information
section.
The architecture for this specific PSoC device family, as shown
in the
Logic Block Diagram
on page 1, consists of four main
areas: PSoC Core, Digital System, Analog System, and System
Resources. The configurable global bus system allows all the
device resources to be combined into a complete custom
system. PSoC CY8C28xxx family devices have up to six I/O
ports that connect to the global digital and analog interconnects,
providing access to up to 12 digital blocks and up to 16 analog
blocks.
32-bit peripherals, which are called user modules. The digital
blocks can be connected to any GPIO through a series of global
buses that can route any signal to any pin.
Figure 2. Digital System Block Diagram
[1]
Port 5
Port 4
Port 3
Port 2
Port 1
Port 0
Digital Clocks
From Core
To System Bus
To Analog
System
DIGITAL SYSTEM
Digital PSoC Block Array
Row Input
Configuration
Row 0
DBC00
DBC01
DCC02
4
DCC03
4
Row Output
Configuration
8
8
Row Input
Configuration
8
Row 1
DBC10
DBC11
DCC12
4
DCC13
4
8
Row Output
Configuration
Row Input
Configuration
Row 2
DBC20
DBC21
DCC22
4
DCC23
4
Row Output
Configuration
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
GOE[7:0]
GOO[7:0]
The PSoC Core
The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
general Purpose I/O (GPIO). The M8C CPU core is a powerful
processor with speeds up to 24 MHz, providing a four MIPS 8-bit
Harvard architecture microcontroller.
Memory encompasses 16K bytes of Flash for program storage,
1K bytes of SRAM for data storage. The PSoC device incorpo-
rates flexible internal clock generators, including a 24 MHz
internal main oscillator (IMO) accurate to 2.5% over temperature
and voltage. A low power 32 kHz internal low speed oscillator
(ILO) is provided for the sleep timer and watch dog timer (WDT).
The 32.768 kHz external crystal oscillator (ECO) is available for
use as a real time clock (RTC) and can optionally generate a
crystal-accurate 24 MHz system clock using a PLL.
PSoC GPIOs provide connections to the CPU, and digital and
analog resources. Each pin’s drive mode may be selected from
8 options, which allows great flexibility in external interfacing.
Every pin also has the capability to generate a system interrupt
on high level, low level, and change from last read.
Digital peripheral configurations include:
■
■
■
■
■
■
■
PWMs (8- and 16-bit, One-shot and Multi-shot capability)
PWMs with Dead band/Kill (8- and 16-bit)
Counters (8 to 32 bit)
Timers (8 to 32 bit)
Full-duplex 8-bit UARTs (up to 3) with selectable parity
Half-duplex 8-bit UARTs (up to 6) with selectable parity
Variable length SPI slave and master
❐
Up to 6 total slaves and masters (8-bit)
❐
Supports 8 to 16 bit operation
I
2
C slave, master, or multi-master (up to 2 available as System
Resources)
IrDA (up to 3)
Pseudo Random Sequence Generators (8 to 32 bit)
Cyclical Redundancy Checker/Generator (16 bit)
Shift Register (2 to 32 bit)
■
■
■
■
■
The Digital System
The Digital System is composed of up to 12 configurable digital
PSoC blocks. Each block is an 8-bit resource that can be used
alone or combined with other blocks to create 8, 16, 24, and
Note
1. CY8C28x52 devices do not have digital block row 2. They have two digital rows with eight total digital blocks.
Document Number: 001-48111 Rev. *P
Page 4 of 87
CY8C28243/CY8C28403/CY8C28413
CY8C28433/CY8C28445/CY8C28452
CY8C28513/CY8C28545
CY8C28623/CY8C28643/CY8C28645
The Analog System
The Analog System is composed of up to 16 configurable analog
blocks, each containing an opamp circuit that allows the creation
of complex analog signal flows. Some devices in this PSoC
family have an analog multiplex bus that can connect to every
GPIO pin. This bus can also connect to the analog system for
analysis with comparators and analog-to-digital converters. It
can be split into two sections for simultaneous dual-channel
processing.
Some of the more common PSoC analog functions (most
available as user modules) are:
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Figure 3. Analog System Block Diagram for CY8C28x45 and
CY8C28x52 Devices
All GPIO
P0[7]
P0[5]
P0[3]
P0[1]
AGNDIn RefIn
P0[6]
P0[4]
P0[2]
P0[0]
P2[6]
P2[3]
P2[1]
Analog Mux
Bus
Analog-to-digital converters (6 to 14-bit resolution, up to 4,
selectable as Incremental or Delta Sigma)
Dedicated 10-bit SAR ADC with sample rates up to 142 ksps
Synchronized, simultaneous Delta Sigma ADCs (up to 4)
Filters (2 to 8 pole band-pass, low pass, and notch)
Amplifiers (up to 4, with selectable gain to 48x)
Instrumentation amplifiers (up to 2, with selectable gain to 93x)
Comparators (up to 6, with 16 selectable thresholds)
DACs (up to 4, with 6 to 9-bit resolution)
Multiplying DACs (up to 4, with 6 to 9-bit resolution)
High current output drivers (up to 4 with 30 mA drive)
1.3 V reference (as a System Resource)
DTMF Dialer
Modulators
Correlators
Peak detectors
Many other topologies possible
P2[4]
P2[2]
P2[0]
Array Input Configuration
ACI0[1:0]
ACI1[1:0]
ACI2[1:0]
ACI3[1:0]
ACI4[1:0]
ACI5[1:0]
Block Array
ACC00
ASC10
ASD20
ACC01
ASD11
ASC21
ACC02
ASC12
ASD22
ACC03
ACE00
ACE01
ASE11
ASD13
ASE10
ASC23
Analog Reference
Interface to
Digital System
RefHi
RefLo
AGND
Reference
Generators
AGNDIn
RefIn
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
Document Number: 001-48111 Rev. *P
Page 5 of 87
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