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PRELIMINARY
CY7C1308DV25C
9 Mbit DDR I SRAM 4-Word
Burst Architecture
Features
n
n
n
n
Functional Description
The CY7C1308DV25C is a 2.5V Synchronous Pipelined SRAM
equipped with DDR I (Double Data Rate) architecture. The
DDR I architecture consists of an SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst counter.
Addresses for Read and Write are latched on alternate rising
edges of the input (K) clock. Write data is registered on the rising
edges of both K and K. Read data is driven on the rising edges
of C and C if provided, or on the rising edge of K and K if C/C are
not provided. Every Read or Write operation is associated with
four words that burst sequentially into or out of the device. The
burst counter takes in the least two significant bits of the external
address and bursts four 36-bit words. Depth expansion is
accomplished with Port Selects for each port. Port Selects allow
each port to operate independently.
Asynchronous inputs include impedance match (ZQ).
Synchronous data outputs (Q, sharing the same physical pins as
the data inputs D) are tightly matched to the two output echo
clocks CQ/CQ, eliminating the need for separately capturing
data from each individual DDR SRAM in the system design.
Output data clocks (C/C) are also provided for maximum system
clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C input clocks. Writes are
conducted with on-chip synchronous self timed write circuitry.
9 Mbit Density (256 Kbit x 36)
250 MHz Clock for High Bandwidth
4-Word Burst to Reduce Address Bus Frequency
Double Data Rate (DDR) Interfaces
(data transferred at 500 MHz at 250 MHz)
Two Input Clocks (K and K) for Precise DDR Timing—SRAM
uses rising edges only
Two Input Clocks (C and C) Account for Clock Skew and Flight
Time Mismatching
Separate Port Selects for Depth Expansion
Synchronous Internally Self-timed Writes
2.5V Core Power Supply with HSTL Inputs and Outputs
Variable Drive HSTL Output Buffers
Expanded HSTL Output Voltage (1.4V to 1.9V)
13 x 15 x 1.4 mm 1.0 mm pitch fBGA package, 165 ball (11 x
15 matrix)
JTAG 1149.1 Compatible Test Access Port
n
n
n
n
n
n
n
n
n
Configuration
CY7C1308DV25C – 256K x 36
Logic Block Diagram
Burst
Logic
16
A
(1:0)
18
A
(17:0)
LD
K
K
CLK
Gen.
Write Add. Decode
Read Add. Decode
Address
A
(17:2)
Register
Write
Reg
Write
Reg
Write
Reg
Write
Reg
256K x 36 Array
36
Output
Logic
Control
Read Data Reg.
144
Vref
R/W
Control
Logic
72
72
Reg.
Reg.
36
Reg.
C
C
CQ
CQ
36
DQ
[35:0]
Cypress Semiconductor Corporation
Document Number: 001-04310 Rev. *D
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised October 12, 2010
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PRELIMINARY
CY7C1308DV25C
Selection Guide
Parameter
Maximum Operating Frequency
Maximum Operating Current
Shaded areas contain advance information.
250 MHz
250
850
200 MHz
200
700
167 MHz
167
600
Unit
MHz
mA
Pin Configuration
CY7C1308DV25C (256K × 36) – 11 × 15 FBGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
TDO
2
DQ27
NC
DQ29
NC
DQ30
DQ31
V
REF
NC
NC
DQ33
NC
DQ35
NC
TCK
3
DQ18
DQ28
DQ19
DQ20
DQ21
DQ22
V
DDQ
DQ32
DQ23
DQ24
DQ34
DQ25
DQ26
A
4
R/W
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
NC
NC
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
A0
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
NC
NC
A1
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
LD
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
NC
DQ17
NC
DQ15
NC
NC
V
REF
DQ13
DQ12
NC
DQ11
NC
DQ9
TMS
11
CQ
DQ8
DQ7
DQ16
DQ6
DQ5
DQ14
ZQ
DQ4
DQ3
DQ2
DQ1
DQ10
DQ0
TDI
GND/144M NC/36M
NC/18M GND/72M
Pin Definitions
Name
DQ
[35:0]
I/O
Input/Output
Synchronous
Description
Data Input/Output Signals.
Inputs are sampled on the rising edge of K and K clocks
during valid Write operations. These pins drive out the requested data during a Read
operation. Valid data is driven out on the rising edge of both the C and C clocks during
Read operations or K and K when in single clock mode. When Read access is deselected,
Q
[35:0]
are automatically tristated.
Synchronous Load.
This input is brought LOW when a bus cycle sequence is to be
defined. This definition includes address and Read/Write direction. All transactions
operate on a burst of 4 data (two clock periods of bus activity).
Address Inputs.
These address inputs are multiplexed for both Read and Write opera-
tions. A0 and A1 are the inputs to the burst counter. These are incremented in a linear
fashion internally. Eighteen address inputs are needed to access the entire memory
array. All the address inputs are ignored when the part is deselected.
Synchronous Read/Write Input.
When LD is LOW, this input designates the access
type (Read when R/W is HIGH, Write when R/W is LOW) for loaded address. R/W must
meet the setup and hold times around edge of K.
Positive Output Clock Input.
C is used in conjunction with C to clock out the Read data
from the device. C and C can be used together to deskew the flight times of various
devices on the board back to the controller. See
Figure 1
on page 5 for further details.
LD
Input
Synchronous
Input
Synchronous
A, A0, A1
R/W
Input
Synchronous
Input Clock
C
Document Number: 001-04310 Rev. *D
Page 2 of 19
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PRELIMINARY
CY7C1308DV25C
Pin Definitions
Name
C
(continued)
I/O
Input Clock
Description
Negative Output Clock Input.
C is used in conjunction with C to clock out the Read data
from the device. C and C can be used together to deskew the flight times of various
devices on the board back to the controller. See
Figure 1
on page 5 for further details.
Positive Input Clock Input.
The rising edge of K is used to capture synchronous inputs
to the device and to drive out data through Q
[35:0]
when in single clock mode. All accesses
are initiated on the rising edge of K.
Negative Input Clock Input.
K is used to capture synchronous inputs being presented
to the device and to drive out data through Q
[35:0]
when in single clock mode.
CQ is Referenced with Respect to C.
This is a free running clock and is synchronized
to the output clock (C) of the DDR I. In the single clock mode, CQ is generated with
respect to K. The timings for the echo clocks are shown in the AC timing table.
CQ is Referenced with Respect to C.
This is a free running clock and is synchronized
to the output clock (C) of the DDR I. In the single clock mode, CQ is generated with
respect to K. The timings for the echo clocks are shown in the AC timing table.
Output Impedance Matching Input.
This input is used to tune the device outputs to the
system data bus impedance. CQ, CQ and Q
[35:0]
output impedance are set to 0.2 x RQ,
where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be
connected directly to V
DD
, which enables the minimum impedance mode. This pin cannot
be connected directly to GND or left unconnected.
TDO for JTAG.
TCK pin for JTAG.
TDI pin for JTAG.
TMS pin for JTAG.
Not Connected to the Die.
Can be tied to any voltage level.
Address Expansion for 18M.
This is not connected to the die.
Address Expansion for 36M.
This is not connected to the die.
Address Expansion for 72M.
This should be tied LOW.
Address Expansion for 144M.
This should be tied LOW.
Reference Voltage Input.
Static input used to set the reference level for HSTL inputs
and outputs as well as AC measurement points.
Power supply inputs to the core of the device.
Ground for the device.
Power supply inputs for the outputs of the device.
All synchronous control (R/W, LD) inputs pass through input
registers controlled by the rising edge of the input clocks (K and
K).
K
Input Clock
K
CQ
Input Clock
Echo Clock
CQ
Echo Clock
ZQ
Input
TDO
TCK
TDI
TMS
NC
NC/18M
NC/36M
GND/72M
GND/144M
V
REF
V
DD
V
SS
V
DDQ
Output
Input
Input
Input
N/A
N/A
N/A
Input
Input
Input-
Reference
Power Supply
Ground
Power Supply
Introduction
Functional Overview
The CY7C1308DV25C is a synchronous pipelined Burst SRAM
equipped with DDR interface.
Accesses are initiated on the positive input clock (K). All
synchronous input timing is referenced from the rising edge of
the input clocks (K and K) and all output timing is referenced to
the rising edge of output clocks (C and C or K and K when in
single clock mode).
All synchronous data inputs (D
[35:0]
) pass through input registers
controlled by the input clocks (K and K). All synchronous data
outputs (Q
[35:0]
) pass through output registers controlled by the
rising edge of the output clocks (C and C or K and K when in
single clock mode).
Read Operations
The CY7C1308DV25C is organized internally as an array of
256K x 36. Accesses are completed in a burst of four sequential
36-bit data words. Read operations are initiated by asserting
R/W HIGH and LD LOW at the rising edge of the Positive Input
Clock (K). The address presented to Address inputs are stored
in the Read address register and the least two significant bits of
the address are presented to the burst counter. The burst
counter increments the address in a linear fashion. Following the
next K clock rise the corresponding 36-bit word of data from this
address location is driven onto the Q
[35:0]
using C as the output
timing reference. On the subsequent rising edge of C the next
36-bit data word from the address location generated by the
burst counter is driven onto the Q
[35:0]
. This process continues
Page 3 of 19
Document Number: 001-04310 Rev. *D
[+] Feedback
PRELIMINARY
CY7C1308DV25C
until all four 36-bit data words are driven out onto Q
[35:0]
. The
requested data is valid 3 ns from the rising edge of the output
clock (C or C, 250 MHz device). To maintain the internal logic,
each Read access must be allowed to complete. Each Read
access consists of four 36-bit data words and takes two clock
cycles to complete. Therefore, Read accesses to the device
cannot be initiated on two consecutive K clock rises. The internal
logic of the device ignores the second Read request. Read
accesses can be initiated on every other K clock rise. Doing so
pipelines the data flow such that data is transferred out of the
device on every rising edge of the output clocks (C and C or K
and K when in single clock mode).
When the read port is deselected, the CY7C1308DV25C first
completes the pending read transactions. Synchronous internal
circuitry automatically tristates the outputs following the next
rising edge of the positive output clock (C). This allows for a
seamless transition between devices without the insertion of wait
states in a depth expanded memory.
identical to the operation if the device had zero skew between
the K/K and C/C clocks. All timing parameters remain the same
in this mode. To use this mode of operation, the user must tie C
and C HIGH at power-on. This function is a strap option and not
alterable during device operation.
DDR Operation
The CY7C1308DV25C enables high performance operation
through high clock frequencies (achieved through pipelining) and
double data rate mode of operation. At slower frequencies, the
CY7C1308DV25C requires a single No Operation (NOP) cycle
when transitioning from a Read to a Write cycle. At higher
frequencies, a second NOP cycle may be required to prevent
bus contention.
If a Read occurs after a Write cycle, address and data for the
Write are stored in registers. The Write information must be
stored because the SRAM can not perform the last word Write
to the array without conflicting with the Read. The data stays in
this register until the next Write cycle occurs. On the first Write
cycle after the Read(s), the stored data from the earlier Write is
written into the SRAM array. This is called a Posted Write.
Write Operations
Write operations are initiated by asserting R/W LOW and LD
LOW at the rising edge of the positive input clock (K). The
address presented to Address inputs are stored in the Write
address register and the least two significant bits of the address
are presented to the burst counter. The burst counter increments
the address in a linear fashion. On the following K clock rise, the
data presented to D
[35:0]
is latched and stored into the 36-bit
Write Data register. On the subsequent rising edge of the
Negative Input Clock (K) the information presented to D
[35:0]
is
also stored into the Write Data Register.This process continues
for one more cycle until four 36-bit words (a total of 144 bits) of
data are stored in the SRAM. The 144 bits of data are then written
into the memory array at the specified location. Therefore, Write
accesses to the device can not be initiated on two consecutive
K clock rises. The internal logic of the device ignores the second
Write request. Write accesses can be initiated on every other
rising edge of the positive input clock (K). Doing so pipelines the
data flow such that 36-bits of data can be transferred into the
device on every rising edge of the input clocks (K and K).
When deselected, the Write port ignores all inputs after the
pending Write operations are completed.
Depth Expansion
Depth expansion requires replicating the LD control signal for
each bank. All other control signals can be common between
banks as appropriate.
Echo Clocks
Echo clocks are provided on the DDR I to simplify data capture
on high-speed systems. Two echo clocks are generated by the
DDR I. CQ is referenced with respect to C and CQ is referenced
with respect to C. These are free-running clocks and are
synchronized to the output clock of the DDR I. In the single clock
mode, CQ is generated with respect to K and CQ is generated
with respect to K. The timings for the echo clocks are shown in
the AC Timing table.
Programmable Impedance
An external resistor, RQ must be connected between the ZQ pin
on the SRAM and V
SS
to allow the SRAM to adjust its output
driver impedance. The value of RQ must be 5X the value of the
intended line impedance driven by the SRAM, The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175Ω and 350Ω
,
with V
DDQ
=1.5V. The
output impedance is adjusted every 1024 cycles to adjust for
drifts in supply voltage and temperature.
Single Clock Mode
The CY7C1308DV25C can be used with a single clock that
controls both the input and output registers. In this mode, the
device recognizes only a single pair of input clocks (K and K) that
control both the input and output registers. This operation is
Document Number: 001-04310 Rev. *D
Page 4 of 19
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