DM74S182 Look-Ahead Carry Generator
August 1986
Revised March 2000
DM74S182
Look-Ahead Carry Generator
General Description
These circuits are high-speed, look-ahead carry genera-
tors, capable of anticipating a carry across four binary
adders or groups of adders. They are cascadable to per-
form full look-ahead across n-bit adders. Carry, generate-
carry, and propagate-carry functions are provided as
shown in the pin designation table.
When used in conjunction with the 181 arithmetic logic unit,
these generators provide high-speed carry look-ahead
capability for any word length. Each DM74S182 generates
the look-ahead (anticipated carry) across a group of four
ALU’s and, in addition, other carry look-ahead circuits may
be employed to anticipate carry across sections of four
look-ahead packages up to n-bits. The method of cascad-
ing circuits to perform multi-level look-ahead is illustrated
under typical application data.
Carry input and output of the ALU’s are in their true form,
and the carry propagate (P) and carry generate (G) are in
negated form; therefore, the carry functions (inputs, out-
puts, generate, and propagate) of the look-ahead genera-
tors are implemented in the compatible forms for direct
connection to the ALU. Reinterpretations of carry functions,
as explained on the 181 data sheet are also applicable to
and compatible with the look-ahead generator. Positive
logic equations for the DM74S182 are:
C
n
+
x
=
G0
+
P0 C
n
C
n
+
y
=
G1
+
P1 G0
+
P1 P0 C
n
C
n
+
z
=
G2
+
P2 G1
+
P2 P1 G0
+
P2 P1 P0 C
n
G
=
G3 (P3
+
G2) (P3
+
P2
+
G1)
(P3
+
P2
+
P1
+
G0)
P
=
P3 P2 P1 P0
Features
s
Typical propagation delay time 7 ns
s
Typical power dissipation 260 mW
Ordering Code:
Order Number
DM74S182N
Package Number
N16E
Package Description
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Connection Diagram
Pin Designations
Designation
G0, G1, G2, G3
P0, P1, P2, P3
C
n
C
n
+
x
, C
n
+
y
,
C
n
+
z
G
P
V
CC
GND
10
7
16
8
Active LOW
Carry Generate Output
Active LOW
Carry Propagate Output
Supply Voltage
Ground
Pin Nos.
3, 1, 14, 5
4, 2, 15, 6
13
12, 11, 9
Function
Active LOW
Carry Generate Inputs
Active LOW
Carry Propagate Inputs
Carry Input
Carry Outputs
© 2000 Fairchild Semiconductor Corporation
DS006474
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DM74S182
Logic Diagram
V
CC
=
PIN 16
GND
=
PIN 8
Typical Application
64-Bit ALU, Full-Carry Look Ahead in Three Levels
A and B inputs, and F outputs of 181 are not shown.
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2
DM74S182
Absolute Maximum Ratings
(Note 1)
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
Storage Temperature Range
7V
5.5V
0°C to
+70°C
−65°C
to
+150°C
Note 1:
The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Recommended Operating Conditions
Symbol
V
CC
V
IH
V
IL
I
OH
I
OL
T
A
Supply Voltage
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Current
LOW Level Output Current
Free Air Operating Temperature
0
Parameter
Min
4.75
2
0.8
−1
20
70
Nom
5
Max
5.25
Units
V
V
V
mA
mA
°C
Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Symbol
V
I
V
OH
V
OL
I
I
I
IH
Parameter
Input Clamp Voltage
HIGH Level
Output Voltage
LOW Level
Output Voltage
HIGH Level
Input Current
Conditions
V
CC
=
Min, I
I
= −18
mA
V
CC
=
Min, I
OH
=
Max
V
IL
=
Max, V
IH
=
Min
V
CC
=
Min, I
OL
=
Max
V
IH
=
Min, V
IL
=
Max
V
CC
=
Max
V
I
=
2.7V
P0, P1 or G3
P3
P2
C
n
G0, G2
G1
I
IL
LOW Level
Input Current
V
CC
=
Max
V
I
=
0.5V
P0, P1 or G3
P3
P2
C
n
G0, G2
G1
I
OS
I
CCH
I
CCL
Short Circuit Output Current
V
CC
=
Max (Note 3)
−40
39
69
Supply Current with Outputs HIGH V
CC
=
Max (Note 4)
Supply Currents with Outputs LOW V
CC
=
Max (Note 5)
2.7
3.4
0.5
1
200
100
150
50
350
400
−8
−4
−6
−2
−14
−16
−100
55
109
mA
mA
mA
mA
Min
Typ
(Note 2)
Max
−1.2
Units
V
V
V
mA
µA
Input Current @ Max Input Voltage V
CC
=
Max, V
I
=
5.5V
Note 2:
All typicals are at V
CC
=
5V, T
A
=
25°C.
Note 3:
Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 4:
I
CCH
is measured with all outputs OPEN, inputs P3 and G3 at 4.5V, and all other inputs grounded.
Note 5:
I
CCL
is measured with all outputs OPEN, inputs G0, G1, and G2 at 4.5V, and all other inputs grounded.
3
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DM74S182
Switching Characteristics
at V
CC
=
5V and T
A
=
25°C
R
L
=
280Ω
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
Parameter
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
From (Input)
To (Output)
GN or PN to C
n
+
x, y, z
GN or PN to C
n
+
x, y, z
GN or PN to G
GN or PN to G
PN to P
PN to P
C
n
to to C
n
+
x, y, z
C
n
to to C
n
+
x, y, z
C
L
=
15 pF
Min
Max
7
7
7.5
10.5
6.5
10
10
10.5
C
L
=
50 pF
Min
Min
10
11
11
14
10
14
13
14
ns
ns
ns
ns
ns
ns
ns
ns
Units
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4
DM74S182 Look-Ahead Carry Generator
Physical Dimensions
inches (millimeters) unless otherwise noted
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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5
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