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TSB41LV06
IEEE 1394a SIX-PORT CABLE TRANSCEIVER/ARBITER
SLLS289 – JANAURY1999
D
D
D
D
D
D
D
D
Fully Supports Provisions of IEEE
1394–1995 Standard for High Performance
Serial Bus
†
and the P1394a Supplement
(Draft 2.0)
Full P1394a Support Includes: Connection
Debounce, Arbitrated Short Reset,
Multispeed concatenation, Arbitration
Acceleration, Fly-by Concatenation, Port
Disable/Suspend/Resume
Provides Six P1394a Fully Compliant Cable
Ports at 100/200/400 Megabits per Second
(Mbits/s)
Cable Ports Monitor Line Conditions for
Active Connection to Remote Node
Power-Down Features to Conserve Energy
in Battery Powered Applications include:
Automatic Device Power-Down during
Suspend, Device Power-Down Pin, Link
Interface Disable via LPS, and Inactive
Ports Powered Down
Logic Performs System Initialization and
Arbitration Functions
Encode and Decode Functions Included for
Data-Strobe Bit Level Encoding
Incoming Data Resynchronized to Local
Clock
D
D
D
D
D
D
D
D
D
D
D
D
Single 3.3 V Supply Operation
Interface to Link Layer Controller Supports
Low Cost TI™ Bus-Holder Isolation and
Optional Annex J Electrical Isolation
Data Interface to Link-Layer Controller
Through 2/4/8 Parallel Lines at 49.152 MHz
Low Cost 24.576-MHz Crystal Provides
Transmit, Receive Data at 100/200/400
Mbits/s, and Link-Layer Controller Clock at
49.152 MHz
Interoperable with Link-Layer Controllers
Using 3.3-V and 5-V Supplies
Interoperable with Other Physical Layers
(PHY) Using 3.3-V and 5-V Supplies
Node Power Class Information Signaling
for System Power Management
Cable Power Presence Monitoring
Separate Cable Bias (TPBIAS) for Each Port
Register Bits Give Software Control of
Contender Bit, Power Class Bits, Link
Active Bit and P1394a Features
Fully Interoperable with FIreWire™ and
i.LINK™ Implementation of IEEE Std 1394
Low Cost, High Performance 100 Pin TQFP
(PZP) Thermally Enhanced Package
description
The TSB41LV06 provides the digital and analog transceiver functions needed to implement a six-port node in
a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The
transceivers include circuitry to monitor the line conditions as needed for determining connection status, for
initialization and arbitration, and for packet reception and transmission. The TSB41LV06 is designed to interface
with a Link Layer Controller (LLC), such as the TSB12LV22, TSB12LV21, TSB12LV31, TSB12LV41, or
TSB12LV01.
The TSB41LV06 requires only an external 24.576 MHz crystal as a reference. An external clock may be
provided instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which generates
the required 393.216 MHz reference signal. This reference signal is internally divided to provide the clock
signals used to control transmission of the outbound encoded Strobe and Data information. A 49.152 MHz clock
signal is supplied to the associated LLC for synchronization of the two chips and is used for resynchronization
of the received data. The power-down (PD) function, when enabled by asserting the PD terminal high, stops
operation of the PLL.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thompson, Limited.
i.LINK is a trademark of Sony Corporation
FireWire is a trademark of Apple Computers Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
©
1999, Texas Instruments Incorporated
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1
TSB41LV06
IEEE 1394a SIX-PORT CABLE TRANSCEIVER/ARBITER
SLLS289 – JANAURY1999
description (continued)
The TSB41LV06 supports an optional isolation barrier between itself and its LLC. When the ISO input terminal
is tied high, the LLC interface outputs behave normally. When the ISO terminal is tied low, internal differentiating
logic is enabled, and the outputs are driven such that they can be coupled through a capacitive or transformer
galvanic isolation barrier as described in IEEE 1394a section 5.9.4. To operate with TI Bus Holder isolation the
ISO on the PHY terminal must be tied HIGH.
Data bits to be transmitted through the cable ports are received from the LLC on two, four or eight parallel paths
(depending on the requested transmission speed) and are latched internally in the TSB41LV06 in
synchronization with the 49.152 MHz system clock. These bits are combined serially, encoded, and transmitted
at 98.304, 196.608, or 392.216 Mbits/s (referred to as S100, S200, and S400 speed, respectively) as the
outbound data-strobe information stream. During transmission, the encoded data information is transmitted
differentially on the TPB cable pair(s), and the encoded strobe information is transmitted differentially on the
TPA cable pair(s).
During packet reception the TPA and TPB transmitters of the receiving cable port are disabled, and the receivers
for that port are enabled. The encoded data information is received on the TPA cable pair, and the encoded
strobe information is received on the TPB cable pair. The received data-strobe information is decoded to recover
the receive clock signal and the serial data bits. The serial data bits are split into two, four or eight bit parallel
streams (depending upon the indicated receive speed), resynchronized to the local 49.152 MHz system clock
and sent to the associated LLC. The received data is also transmitted (repeated) on the other active (connected)
cable ports.
Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during
initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the
arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this
common-mode voltage is used during arbitration to set the speed of the next packet transmission. In addition,
the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of the
remotely supplied twisted-pair bias voltage.
The TSB41LV06 provides a 1.86 V nominal bias voltage at the TPBIAS terminal for port termination. The PHY
contains two independent TPBIAS circuits. This bias voltage, when seen through a cable by a remote receiver,
indicates the presence of an active connection. This bias voltage source must be stabilized by an external filter
capacitor of 1
µF.
The line drivers in the TSB41LV06 operate in a high-impedance current mode, and are designed to work with
external 110
Ω
line-termination resistor networks in order to match the 110-Ω cable impedance. One network
is provided at each end of a twisted-pair cable. Each network is composed of a pair of series-connected 56-Ω
resistors. The midpoint of the pair of resistors that is directly connected to the twisted pair A terminals is
connected to its corresponding TPBIAS voltage terminal. The midpoint of the pair of resistors that is directly
connected to the twisted-pair B terminals is coupled to ground through a parallel R-C network with
recommended values of 5 kΩ and 220 pF. The values of the external line termination resistors are designed
to meet the standard specifications when connected in parallel with the internal receiver circuits. An external
resistor connected between the R0 and R1 terminals sets the driver output current, along with other internal
operating currents. This current setting resistor has a value of 6.3-kΩ
±0.5%.
This may be accomplished by
placing a 6.34-kΩ
±0.5%
resistor in parallel with a 1-MΩ resistor.
When the power supply of the TSB41LV06 is 0 V while the twisted-pair cables are connected, the TSB41LV06
transmitter and receiver circuitry will present a high impedance to the cable and will not load the TPBIAS voltage
at the other end of the cable.
2
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TSB41LV06
IEEE 1394a SIX-PORT CABLE TRANSCEIVER/ARBITER
SLLS289 – JANAURY1999
When the TSB41LV06 is used with one or more of the ports not brought out to a connector, the twisted–pair
terminals of the unused ports must be terminated for reliable operation. For each unused port, the TPB+ and
TPB– terminals should be tied together and then pulled to ground, or the TPB+ and TPB– terminals should be
connected to the suggested termination network. The TPA+ and TPA– and TPBIAS terminals of an unused port
may be left unconnected. The TPBias terminal should be connected to a 1-µF capacitor to ground or left floating.
The TESTM, SE, and SM terminals are used to set up various manufacturing test conditions. For normal
operation, the TESTM terminal should be connected to V
DD
, SE should be tied to ground through a 1-kΩ resistor,
while SM should be connected directly to ground.
Four package terminals are used as inputs to set the default value for four configuration status bits in the self–ID
packet, and are hardwired high or low as a function of the equipment design. The PC0–PC2 terminals are used
to indicate the default power-class status for the node (the need for power from the cable or the ability to supply
power to the cable). See Table 9 for power-class encoding. The C/LKON terminal is used as an input to indicate
that the node is a contender for either isochronous resource manager (IRM) or bus manager (BM).
The PHY supports suspend/resume as defined in the IEEE P1394a specification. The suspend mechanism
allows pairs of directly–connected ports to be placed into a low power conservation state while maintaining a
port–to–port connection between 1394 bus segments. While in a low–power state, a port is unable to transmit
or receive data transaction packets. However, a port in a low power state is capable of detecting connection
status changes and detecting incoming TPBias. When all six ports of the TSB41LV06 are suspended all circuits
except the bandgap reference generator and bias detection circuits are powered down resulting in significant
power savings. For additional details of suspend/resume operation refer to the P1394a specification. The use
of suspend/resume is recommended for new designs.
The port transmitter and receiver circuitry is disabled during power-down (when the PD input terminal is
asserted high), during reset (when the RESET input terminal is asserted low), when no active cable is connected
to the port, or when controlled by the internal arbitration logic. The TPBIAS is disabled during power–down,
during reset, or when the port is disabled as commanded by the LLC.
The CNA (cable-not-active) terminal provides a high output when all twisted-pair cable ports are disconnected,
and can be used along with LPS to determine when to power–down the TSB41LV06. The CNA output is not
debounced. In a PD terminal initiated power down, the CNA detection circuitry remains enabled.
The LPS (link power status) terminal works with the C/LKON terminal to manage the power usage in the node.
The LPS signal from the LLC indicates to the PHY that the LLC is powered up and active. During LLC
power-down mode, as indicated by the LPS input being low for more than 2.6
µs,
the TSB41LV06 deactivates
the PHY-LLC interface to save power. The TSB41LV06 will continue the necessary repeater function required
for network operation during this low power state.
If the PHY receives a link-on packet from another node, the C/LKON terminal is activated to output a
square-wave signal. The LLC recognizes this signal, reactivates any powered-down portions of the LLC, and
notifies the PHY of its power-on status via the LPS terminal. The PHY confirms notification by deactivating the
square-wave signal on the C/LKON terminal, and then enables the PHY-link interface.
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3
TSB41LV06
IEEE 1394a SIX-PORT CABLE TRANSCEIVER/ARBITER
SLLS289 – JANAURY1999
functional block diagram
CPS
LPS
ISO
CNA
SYSCLK
LREQ
CTL0
CTL1
D0
D1
D2
D3
D4
D5
D6
D7
PC0
PC1
PC2
C/LKON
Cable Port 2
Arbitration
and
Control State
Machine
Logic
TPA1+
TPA1–
Cable Port 1
TPB1+
TPB1–
TPA2+
TPA2–
TPB2+
TPB2–
TPA3+
TPA3–
Cable Port 3
R0
R1
TPBIAS0
TPBIAS1
TPBIAS2
TPBIAS3
TPBIAS4
TPBIAS5
Cable Port 5
TPA5+
TPA5–
TPB5+
TPB5–
XI
Crystal Oscillator,
PLL System,
and Clock
Generator
XO
FILTER0
FILTER1
Bias Voltage
AND
Current
Generator
TPB3+
TPB3–
TPA4+
TPA4–
Cable Port 4
TPB4+
TPB4–
Link
Interface
I/O
Received
Data
Decoder/
Retimer
Cable Port 0
TPB0+
TPB0–
TPA0+
TPA0–
PD
RESET
Transmit
Data
Encoder
4
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