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MV1445
PRELIMINARY INFORMATION
DS3109 2.2
MV1445
COMBINED PCM HDB3 DECODER, DIGITAL CLOCK REGENERATOR
AND TIMESLOT ZERO RECEIVER
The MV1445 combines the HDB3 Decoder, Digital Clock
Regnerator and Timeslot Zero Receiver functions required by
a 2.048Mbit 30 channel PCM transmission link operating in
accordance with the appropriate CCITT Recommendations
and forms part of the GPS 2Mbit PCM signalling series of
devices. The circuit is fabricated in CMOS and operates from a
single +5V supply.
The HDB3 Decoder section of the MV1445 is responsible
for decoding the incoming 2.048Mbit HDB3 encoded pseudo-
ternary PCM data stream back into NRZ binary form. This
decoding is carried out in accordance with Annex A to CCITT
Recommendation G.703.
In order to perform this process, the HDB3 Decoder
requires a 2.048MHz clock signal to be recovered from the
incoming HDB3 data stream. This clock regeneration may be
carried out externally using a tuned circuit or internally using
the on-chip Digital Clock Regenerator. This digital clock
regenerator circuit continuously re-synchronises a divide-by-8
counter being clocked at 16.384MHz to the incoming HDB3
data stream and performs in accordance with the tolerance to
input jitter specification of CCITT Recommendation G.823.
The Timeslot Zero Receiver function searches for the
CCITT Frame Alignment signal in the NRZ data stream being
output by the HDB3 Decoder and when this pattern is detected
the receiver synchronises itself to it in accordance with the
Frame Alignment strategy detailed in CCITT Recommendation
G.732. Once frame alignment has been achieved the Timeslot
Zero Receiver produces various timing outputs for the use of
external circuitry and extracts the user data bits of timeslot
zero.
GND1
RXD1
RXD2
LIA
NC
DV
Q-DC
Q1S
Q1N
CLK
FRS13
FRS15
RAI
CRC
RST
NC
SA
STM
ER
GND2
1
2
3
4
5
6
7
8
9
40
39
38
37
36
35
34
33
32
VDD
NC
Q8N
Q7N
Q6N
Q5N
Q4N
Q3N
NC
RESET AIS
AIS
TSZ
TZS
MODE
NC
NC
X OUT/CDR
CCR
X IN
CK8
10
MV
31
1445
11
30
29
28
27
26
25
24
23
22
21
12
13
14
15
16
17
18
19
20
DG40, DP40
GND1
RXD2
RXD1
VDD
Q8N
Q7N
6
5
4
3
2
1
FEATURES
s
Single +5V supply.
s
All Inputs and Outputs TTL compatible.
s
HDB3 Decoding carried out in accordance with CCITT
Recommendation G.703.
s
Provides HDB3 Error Monitor, Loss of Input Alarm and AIS
Monitor.
s
On-chip digital clock regenerator operates in accordance
with tolerance to input jitter specification of CCITT
Recommendation G.823.
s
Receiver Frame Synchronisation carried out in accordance
with CCITT Recommendation G.732.
s
Provides Alarm Outputs for Reception of Corrupted
Alignment word and Loss of Frame Alignment.
s
Extracts the International Spare Bits from Alternate
Frames or from Frames 13 and 15 of the CCITT CRC-4
multiframe.
NC
DV
Q-DC
Q1S
Q1N
CLK
FRS13
FRS15
RAI
CRC
RST
7
8
9
10
11
12
13
14
15
16
44 43 42 41 40
39
38
37
36
35
Q6N
LIA
NC
NC
NC
Q5N
Q4N
Q3N
RESET AIS
AIS
TSZ
TZS
MODE
NC
NC
NC
MV
1445
34
33
32
31
30
17
29
18 19 20 21 22 23 24 25 26 27 28
X OUT/CDR
NC
NC
STM
ER
CK8
X IN
CCR
GND2
NC
SA
HG44, HP44
Fig. 1 Pin connections - top view
1
MV1445
AIS
DV
LIA
Q-DC
ER
SA
RAI
RESET AIS
RXD1
HDB3 Decoder,
Error and AIS
Circuits
Q8N
Q7N
Q6N
Q5N
RXD2
Q4N
Timeslot
Zero
Receiver
X IN
Q3N
Q1N
Q1S
Digital
Clock
Regenerator
TSZ
TZS
CCR
CK8
X OUT/CDR
ABSOLUTE MAXIMUM RATINGS
The absolute maximum ratings are limiting values above
which operating life may be shortened or specified parameters
may be degraded.
MODE
CLK
Fig. 2 Block diagram
zeroes, the last zero is substituted by a mark of the same
polarity of the previous mark, thus breaking the Alternate Mark
Inversion (AMI) code. This mark is termed a violation. In
addition, the first zero may also be substituted by a mark if the
last mark and last violation are of the same polarity. This mark
does not violate the AMI code and ensures that successive
violations alternate in polarity and as such introduce no DC
component to the HDB3 signal.
The HDB3 Decoder synchronously decodes the data on its
RXD input pins into NRZ form under control of a 2.048MHz
system clock. There is a 5 clock period delay between the
HDB3 data being clocked in from the RXD inputs and the NRZ
data appearing on the Q-DC output. In addition to the basic
HDB3 decoding the circuit also provides three alarm outputs.
The first of these alarms is DV (Double Violation) and a logic
high on this output denotes that two successive violations have
been received with the same polarity, thus violating the HDB3
decoding laws. The second alarm, LIA (Loss of Input Alarm), is
used to denote that 11 consecutive zeroes have been received
on the RXD inputs. The third alarm output is AIS (Alarm
Indication Signal). This output will go high if less than 3
decoded zeros have been detected in the preceding RESET
AIS=1 period (i.e. between RESET AIS=0 pulses) and as such
this alarm can be used to detect the CCITT Alarm Indication
Signal. The timing diagrams of the HDB3 Decoder circuit are
shown in Fig. 3.
Digital Clock Regenerator
In order to decode the incoming HDB3 data stream the
HDB3 decoder requires a 2.048MHz clock to be recovered
from the incoming data stream. This may either be produced
externally using a tuned circuit or internally using the on-chip
digital clock regenerator.
RST
FRS15
FRS13
CRC
GND1
VDD
GND2
STM
ELECTRICAL RATINGS
Supply Voltage
Input Voltage
Output Voltage
-0.5V to +7V
-0.5V to VDD +0.5V
-0.5V to VDD +0.5V
FUNCTIONAL DESCRIPTION
The MV1445 combines the HDB3 Decoder, Digital Clock
Regenerator and Timeslot Zero Receiver functions required by
a 2.048Mbit 30 channel PCM transmission link operating in
accordance with the appropriate CCITT Recommendations.
The block diagram of the MV1445 is shown in Fig.2 and the
function of each block is now described separately.
HDB3 Decoder
The HDB3 decoder circuit is responsible for converting the
2.048Mbit HDB3 encoded pseudo-ternary PCM data stream
on its inputs, RXD1 and RXD2, back in to NRZ binary form to
be output to external circuitry and the Timeslot Zero Receiver.
This conversion is carried out in accordance with the HDB3
coding laws specified in CCITT Recommendation G.703,
Annex A.
High Density Bipolar 3 (HDB3) is a ternary transmission
code in which the number of consecutive zeros which may
occur is restricted to three, to ensure adequate clock recovery
at the receiver. In any sequence of four consecutive binary
2
MV1445
Selection between these 2 recovery modes is carried out
by the MODE control pin, and with MODE high, internal clock
recovery is selected.
When external clock recovery is selected, a logical ‘OR’
function of the inverted HDB3 inputs is output on the X OUT/
CDR pin for the use of the external clock recovery circuit. The
2.048MHz clock signal thus regenerated is then input back to
the MV1445 on the CLK I/O pin.
In internal clock recovery mode, the digital clock
regenerator requires either a 16.384MHz clock signal to be
input to the X IN pin or a 16.384MHz crystal to be connected
between pins X IN and X OUT/CDR. The 16.384MHz clock
signal thus produced is used to clock a divide-by-8 counter to
produce the recovered 2.048MHz system clock. This counter
is continuously re-synchronised to the incoming data stream
and attempts to choose the 16.384MHz clock edge furthest
from the falling edge of either of the RXD inputs to use as the
rising edge of the 2MHz recovered clock, giving the highest
tolerance to incoming jitter. This circuit performs in full
compliance with the tolerance to input jitter specification of
CCITT Recommendation G.823. The regenerated clock thus
produced is input to the HDB3 Decoder and Timeslot Zero
Receiver circuits and is also output to external circuitry on the
CLK I/O pin.
Timeslot Zero Receiver
The Timeslot Zero Receiver circuit is responsible for
searching for and locking on to the CCITT Frame Alignment
Signal present in timeslot zero of the NRZ PCM data stream
being decoded by the HDB3 Decoder. This process is carried
out in accordance with the loss and recovery of frame
alignment strategy described in CCITT Recommendation
G.732. Once frame alignment has been achieved the Timeslot
Zero Receiver circuit outputs various timing reference signals
for the synchronisation of external circuitry. These timing
outputs will all free run if frame synchronisation is
subsequently lost. In addition, a control input, RST, may be
used to reset this synchronisation process, forcing the receiver
out of frame alignment.
The Timeslot Zero Receiver circuit produces 4 timing
outputs for use by external circuitry if required. The first of
these timing outputs is TSZ which is an 8 clock period long,
high going pulse masking the position of timeslot zero and
facilitates the frame alignment of external circuitry. The second
timing output, TZS, is a 4KHz signal which changes state once
per frame, one clock period after the end of timeslot zero, and
is high during sync frames to allow sync and non-sync frames
to be distinguished. The third timing output, CCR, is a low
going pulse, one clock period wide, occurring during bit 1,
timeslot 1 of sync frames. The final timing output, CK8, is an
8KHz signal going low at the end of bit 7 of each timeslot zero
and high at the end of bit 7 in each timeslot 16.
In addition to these timing outputs, two alarm outputs are
provided to indicate errors in the incoming data stream. The
first of these alarms, ER, goes high for one frame following a
sync frame in which a corrupted FAS was detected when the
receiver is in sync. Three consecutive alarms of this type will
put the receiver out of sync. The second alarm, SA, goes high
to indicate that the Timeslot Zero Receiver is out of frame
alignment.
In addition to the frame synchronisation process, the
Timeslot Zero Receiver is also responsible for extracting the
user data bits of non-sync words and the two International /
CRC bits of timeslot zero. The user data bits present in bits 3 to
8 of timeslot zero of non-sync frames are extracted and output
on the Q3N-Q8N parallel data outputs. The third bit of non-
sync words, Q3N, is used as the remote alarm bit in 2Mbit
PCM systems and a third alarm output, RAI, is derived from
this bit. This alarm is a persistence checked version of Q3N
which goes high when two consecutive Q3N bits have been
received high whilst the receiver is in sync. The Timeslot Zero
Receiver also extracts the data present in bit 1 of timeslot zero
under control of the CRC input. This input selects between
CCITT CRC-4 and non-CRC-4 modes of operation. In non-
CRC-4 mode, the international spare bits are extracted from bit
1 of all sync and non-sync frames and output on pins Q1S and
Q1N respectively. In CRC-4 mode, these data outputs are
extracted from bit 1 of frames 13 and 15 of the CCITT CRC-4
multiframe structure respectively. In order to accomplish this,
two timing inputs, FRS13 and FRS15, are required in CRC-4
mode. These inputs are required to be high during bit 8 of the
appropriate frame, low during bit 8 of any other non-sync frame
and any state elsewhere. The timing diagrams for the Timeslot
Zero Receiver are shown in Fig.4.
3
MV1445
RXD1
RXD2
XOUT/CDR
CLK
Q-DC
Notes:-
B
B
B
V
B
B
B
B
B
B
5 Clock Periods
1) The Decoded NRZ output is delayed by 5 clock periods with respect to the HDB3 inputs.
2) The diagram assumes the last violation occured on RXD2.
3) B is HDB3 mark, V is a HDB3 violation.
Decoder waveforms
RXD1
RXD2
CLK
DV
Notes:-
B
B
B
V
B
B
V
V
B
1 Clock Period
1)There is a single period delay between detection of an error and the rising edge of DOUBLE VIOLATION
2) The diagram assumes the last violation occured on RXD2.
3) B is HDB3 mark, V is a HDB3 violation.
HDB3 Double violation waveforms
RXD1
RXD2
CLK
LIA
Note:-
1
2
3
4
5
6
7
8
9
10
11
1 Clock Period
1)The 'LOSS OF INPUT' is delayed by a single clock period with respect to the incoming HDB3 waveforms.
Loss of input violations
CLK
Q-DC
RESET AIS
AIS
AIS and RESET AIS waveforms
Fig. 3 HDB3 Decoder timing
4
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