HD61102
(Dot Matrix Liquid Crystal Graphic
Display Column Driver)
Description
HD61102 is a column (segment) driver for dot
matrix liquid crystal graphic display systems. It
stores the display data transferred from a 8-bit
micro-controller in internal display RAM and
generates dot matrix liquid crystal driving signals.
Each bit data of display RAM corresponds to
on/off state of each dot of a liquid crystal display
to provide more flexible than character display.
As it is internally equipped with 64 output drivers
for display, it is available for liquid crystal graphic
displays with many dots.
The HD61102, which is produced by the CMOS
process, can complete a portable battery drive
equipment in combination with a CMOS micro-
controller, utilizing the liquid crystal display’s low
power dissipation.
Moreover it can facilitate dot matrix liquid crystal
graphic display system configuration in combina-
tion with the row (common) driver HD61103A.
Features
• Dot matrix liquid crystal graphic display column
driver incorporating display RAM
• RAM data direct display by internal display
RAM
— RAM bit data 1: On
•
•
•
•
•
— RAM bit data 0: Off
Internal display RAM address counter: Preset,
increment
Display RAM capacity: 512 bytes (4096 bits)
8-bit parallel interface
Internal liquid crystal display driver circuit: 64
Display duty:
— Combination of frame control signal and
data latch synchronization signal make it pos-
sible to select static or optional duty cycle
Wide range of instruction function:
— Display data read/write, display on/off, set
address, set display start line, read status
Lower power dissipation: during display 2 mW
max
Power supply
— V
CC
: +5 V ± 10%
— V
EE
: 0 V to –10 V
Liquid crystal display driving level: 15.5 V max
CMOS process
•
•
•
•
•
Ordering Information
Type No.
HD61102RH
Package
100-pin plastic QFP (FP-100)
HD61102
Pin Arrangement
Y42
Y41
Y40
Y39
Y38
Y37
Y36
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
Y25
Y24
Y23
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
ADC
M
V
CC
V4R
V3R
V2R
V1R
V
EE2
Y64
Y63
Y62
Y61
Y60
Y59
Y58
Y57
Y56
Y55
Y54
Y53
Y52
Y51
Y50
Y49
Y48
Y47
Y46
Y45
Y44
Y43
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
FRM
E
ø1
ø2
CL
D/I
R/W
RST
CS1
CS2
CS3
NC
DY
NC
DB7
DB6
DB5
DB4
DB3
DB2
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DB1
DB0
GND
V4L
V3L
V2L
V1L
V
EE1
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
(Top view)
715
716
V
CC
GND
V
EE1
V
EE2
M
ADC
9
9
XY address counter
V1L
V2L
V3L
V4L
Instruction
register
1
2
3
8
4096 bit
8
6
Z address counter
6
Display start
line register
Display
ON/OFF
6
64
Display data RAM
Input register
1
2
3
Y1
Y2
Y3
64
Liquid crystal display
driver circuit
Display data latch
Output register
62
63
64
62
63
64
Y62
Y63
Y64
Busy
flag
V1R
V2R
V3R
V4R
CL
FRM
HD61102
Block Diagram
Interface control
3
8
I/O buffer
CS1, CS2,
CS3
R/W
D/I
E
DB0–DB7
8
8
DY
RST
ø1
ø2
HD61102
Terminal Functions
Terminal
Name
V
CC
GND
Number of
Terminals
2
I/O
Connected
to
Power supply
Functions
Power supply for internal logic.
Recommended voltage is:
GND = 0 V
V
CC
= +5 V ± 10%
V
EE1
V
EE2
2
Power supply
Power supply for liquid crystal display drive circuit.
Recommended power supply voltage is V
CC
–15 to
GND. Connect the same power supply to V
EE1
and
V
EE2
.
V
EE1
and V
EE2
are not connected to each other in
the LSI.
V1L, V1R
V2L, V2R
V3L, V3R
V4L, V4R
8
Power supply
Power supply for liquid crystal display drive.
Apply the voltage specified for the liquid crystals
within the limit of V
EE
through V
CC
.
V1L (V1R), V2L (V2R): Selected level
V3L (V3R), V4L (V4R): Non-selected level
Power supplies connected with V1L and V1R (V2L &
V2R, V3L & V3R, V4L & V4R) should have the
same voltages.
CS1
CS2
CS3
3
I
MPU
Chip selection
Data can be input or output when the terminals are
in the following conditions:
Terminal name
Condition
E
1
I
MPU
Enable
At write (R/W = low): Data of DB0 to DB7 is latched
at the fall of E.
At read (R/W = high): Data appears at DB0 to DB7
while E is high.
R/W
1
I
MPU
Read/write
R/W = High: Data appears at DB0 to DB7 and can
be read by the MPU when E = high,
CS1, CS2
= low and CS3 = high.
R/W = Low: DB0 to DB7 accepted at fall of E when
CS1, CS2
= low and CS3 = high.
D/I
1
I
MPU
Data/instruction
D/I = High:
D/I = Low:
Indicates that the data of DB0 to DB7
is display data.
Indicates that the data of DB0 to DB7
is display control data.
CS1
L
CS2
L
CS3
H
717
HD61102
Terminal
Name
ADC
Number of
Terminals
1
I/O
I
Connected
to
V
CC
/GND
Functions
Address control signal determine the relation
between Y address of display RAM and terminals
from which the data is output.
ADC = High: Y1–$0, Y64–$63
ADC = Low: Y64–$0, Y1–$63
DB0–DB7
M
FRM
8
1
1
I/O
I
I
MPU
HD61103A
HD61103A
Data bus, three-state I/O common terminals.
Switch signal to convert liquid crystal drive
waveform into AC.
Display synchronous signal (frame signal). Presets
the 6-bit display line counter and synchronizes a
common signal with the frame timing when the FRM
signal becomes high.
Synchronous signal to latch display data. The rising
edge of the CL signal increments the display output
address counter and latches the display data.
2-phase clock signal for internal operation. The ø1
and ø2 clocks are used to perform operations (I/O of
display data and execution of instructions) other
than display.
Liquid crystal display column (segment) drive output.
These pins output light on level when 1 is in the
display RAM, and light off level when 0 is in it.
Relation among output level, M, and display data (D)
is as follows:
M
1
0
CL
1
I
HD61103A
ø1, ø2
1
I
HD61103A
Y1–Y64
64
O
Liquid crystal
display
D
Output
level
1
0
1
0
V1 V3 V2 V4
RST
1
I
MPU or
external CR
The following registers can be initialized by setting
the
RST
signal to low level:
1. On/off register set to 0 (display off)
2. Display start line register set to line 0 (displays
from line 0)
After releasing reset, this condition can be changed
only by instruction.
DY
NC
1
2
O
Open
Open
Output terminal for test. Normally, don’t connect any
lines to this terminal.
Unused terminals. Don’t connect any lines to these
terminals.
Note: 1 corresponds to high level in positive logic.
718
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