Cover
88F5182
Feroceon
®
Storage
Networking SoC
Datasheet
Doc. No. MV-S103345-00, Rev. E
April 29, 2008, Preliminary
Marvell.
Moving Forward Faster
Document Classification: Proprietary Information
88F5182
Datasheet
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Doc. No. MV-S103345-00 Rev. E
Page 2
Document Classification: Proprietary Information
Copyright © 2008 Marvell
April 29, 2008, Preliminary
88F5182 Feroceon
®
Storage Networking SoC
Datasheet
PRODUCT OVERVIEW
The Marvell
®
88F5182 device is a high-performance,
highly integrated, Storage Networking System Engine. It
is based on the Marvell Feroceon
®
CPU core, which is
fully compliant with the ARMv5TE.
•
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Out-of-order execution for increased performance
In-order retire via a Reordering Buffer (ROB)
Branch Prediction Unit
Supports JTAG/ARM Multi-ICE
Supports both Big and Little Endian modes
FEATURES
High-performance integrated controller
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High-performance Feroceon CPU core with
integrated 32/32 KB I/D L1 cache, running at up to
500 MHz
•
High bandwidth dual-port memory controller
(16-/32-bit DDR1/DDR2 SDRAM)
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Single PCI Express (x1) port with integrated PHY
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Single 32-bit PCI2.2 66 MHz port
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Two SATA 2.0 ports with integrated 3 Gbps SATA II
PHYs
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Single Gigabit Ethernet MAC (10/100/1000 Mbps)
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Two USB 2.0 ports with integrated PHY
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Security Cryptographic Engine
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Two-Wire Serial Interface (TWSI)
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Two UART ports
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16-bit device bus with up to four chip selects
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NAND Flash Support
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Integrated DMA engine (four channels)
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XOR engine for RAID applications
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26 multi-purpose pins
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Interrupt controller
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Timers
Marvell
®
Feroceon
®
CPU core
•
500 MHz with DDR1/DDR2 at 166 MHz
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400 MHz with DDR2 at 200 MHz
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32-bit and 16-bit RISC architecture
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Compliant with v5TE architecture as published in
the ARM Architect Reference Manual, Second
Edition
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Includes MMU to support virtual memory features
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MPU can be used instead when not using MMU
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32-KB I-Cache and 32-KB D-Cache
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64-bit internal data bus
DDR1/DDR2 SDRAM controller
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DDR SDRAM with a clock ratio of 1:1, 1:2, 1:3, or
1:4 between the DDR SDRAM and the Feroceon
CPU core, respectively
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16-/32-bit interface
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DDR1 at up to 333 MHz
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DDR2 at up to 400 MHz
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Supports up to two dual-sided DIMMs
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Supports DDR components of x8 and x16
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Dual channel memory controller
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Reduced CPU to DDR SDRAM latency
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SSTL 2.5V I/Os in DDR1, 1.8V I/Os in DDR2
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Supports four DDR SDRAM banks (CSs)
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DDR1 supports device densities of 128, 256,
512 Mbits
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DDR2 supports device densities of 256, 512 Mbits
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Up to 1 GB (32-bit interface) and 0.5 GB (16-bit
interface) total memory space
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Supports DDR SDRAM bank interleaving between
all DDR SDRAM banks (both the physical banks,
and the four internal banks of the DDR SDRAM
devices)
•
Supports up to 16 open pages (page per bank)
•
Supports configurable DDR SDRAM timing
parameters
•
Supports up to 32-byte burst per single DDR
SDRAM access
•
Single ended DQS in DDR2
•
DDR1/DDR2 pad auto calibration
•
Support DDR2 On Die Termination (ODT)
PCI Express interface (x1)
•
PCI Express Base 1.0a compatible
•
Integrated low power SERDES PHY, based on
proven Marvell SERDES technology
•
Root Complex port
•
Can be configured also as an Endpoint port
•
x1 link width
Copyright © 2008 Marvell
April 29, 2008, Preliminary
Document Classification: Proprietary Information
Doc. No. MV-S103345-00 Rev. E
Page 3
88F5182
Datasheet
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2.5 GHz/s signalling
Lane polarity reversal support
Maximum payload size of 128 bytes
Single Virtual Channel (VC-0)
Replay buffer support
Extended PCI Express configuration space
Advanced Error Reporting (AER) support
Power management: L0s and software L1 support
Interrupt emulation message support
Error message support
•
Vital Product Data (VPD) support
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PCI Power Management (PMG) support
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Message Signal Interrupts (MSI) support
SATA II interface (2 ports)
•
Integrates Marvell 3 Gbps (Gen2i) SATA PHY
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Compliant with SATA II Phase 1 specifications
- Supports SATA II Native Command Queuing
(NCQ), up to 128 outstanding commands per
port
- First party DMA (FPDMA) full support
- Backwards compatible with SATA I devices
•
Supports SATA II Phase 2 advanced features
- 3 Gbps (Gen2i) SATA II speed
- Port Multiplier (PM)—Performs FIS-Based
Switching as defined in SATA working group PM
definition
- Port Selector (PS)—Issues the protocol-based
OOB sequence to select the active host port
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Supports device 48-bit addressing
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Supports ATA Tag Command Queuing
SATA II Host Controller
•
Enhanced-DMA [EDMA] per SATA port
- Automatic command execution without host
intervention
- Command queuing support, for up to 128
outstanding commands
- Separate SATA request/response queues
- 64-bit addressing support for descriptors and
data buffers in system memory
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Read ahead
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Advanced interrupt coalescing
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Target mode operation—Two 88F5182 devices can
be attached through Serial-ATA ports, enabling
data communication between different 88F5182
devices.
•
Advanced drive diagnostics via the ATA SMART
command
Integrated single GbE (10/100/1000) MAC
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Supports 10/100/1000 Mbps
•
MII, GMII, or RGMII Interface
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Proprietary 200 Mbps Marvell MII (MMII) interface
•
Dedicated DMA for data movement between
memory and port
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Priority queuing on receive based on DA, VLAN
Tag, and IP TOS
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Layer 2/3/4 frame encapsulation detection
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TCP/IP checksum on receive and transmit
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DA address filtering
PCI Express master specific features
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Single outstanding read transaction
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Maximum read request of up to 128 bytes
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Maximum write request of up to 128 bytes
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Up to four outstanding read transactions in
Endpoint mode
PCI Express target specific features
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Supports up to eight read request transactions
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Maximum read request size of 4 KB
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Maximum write request of 128 bytes
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Supports PCI Express access to all of the device’s
internal registers
32-bit PCI interface
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66 MHz PCI 2.2 compliant interface
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3.3V I/Os, 5V tolerant
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Supports 64-bit addressing via DAC transactions
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Configurable PCI arbiter for up to six masters
PCI master specific features
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Supports all PCI cycles
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Host to PCI bridge—translates CPU cycles to PCI
memory, I/O, or configuration cycles
•
Supports DMA bursts between PCI and memory
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Supports transaction combining to unlimited PCI
burst
PCI target specific features
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Supports all PCI cycles
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Supports programmable aggressive read prefetch
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Supports unlimited burst write with zero wait states
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Supports up to four delayed reads
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Supports PCI access to all of the device’s internal
registers
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PCI address remapping to local memory
PICMG Compact PCI Hot-Swap ready
PCI “Plug and Play” support
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Plug and Play compatible configuration registers
•
PCI configuration registers that are accessible from
both the Feroceon CPU core and PCI
Doc. No. MV-S103345-00 Rev. E
Page 4
Document Classification: Proprietary Information
Copyright © 2008 Marvell
April 29, 2008, Preliminary
Features
USB 2.0 ports (2 ports)
•
Each port can serve as a peripheral or host
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USB 2.0 compliant
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Integrated USB 2.0 PHY
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EHCI compatible as a host
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As a host, supports direct connection to all
peripheral types (LS, FS, HS)
•
As a peripheral, connects to all host types (HS, FS)
and hubs
•
Up to four independent endpoints supporting
control, interrupt, bulk, and isochronous data
transfers
•
Dedicated DMA for data movement between
memory and port
Two-Wire Serial Interface (TWSI)
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Master/slave operation
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Serial ROM initialization
Two UART interfaces
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16550 UART compatible
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Two pins for transmit and receive operations
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Two pins for modem control functions
Device bus controller
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8-/16-bit width
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166 MHz clock frequency
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3.3V I/Os
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Supports many types of standard memory devices
such as FLASH and ROM
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Four chip selects with programmable timing
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Optional external wait-state support
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Boot ROM support
NAND Flash support
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Glueless interface to CE don’t care NAND Flash
through the device bus interface
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Glueless interface to CE care NAND Flash through
the device bus and MPP interfaces
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Boot from NAND Flash when the 1st block, placed
on 00h block address, is guaranteed to be a valid
block with no errors
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Support read bursts of up to 128 bytes
Four channel Independent DMA controller
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Chaining via linked-lists of descriptors
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Moves data from any to any interface
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Supports increment or hold on both source and
destination address
Two XOR DMAs
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Useful for RAID application
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Supports XOR operation on up to eight source
blocks
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Supports CRC-32 calculation
Cryptographic engine
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Hardware implementation on encryption and
authentication engines to boost packet processing
speed
•
Dedicated DMA to feed the hardware engines with
data from internal SRAM memory
•
Implements AES, DES and 3DES encryption
algorithms
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Implements SHA1 and MD5 authentication
algorithms
26 multi-purpose pins dedicated for peripheral
functions and general purpose I/O
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Each pin can be configured independently
•
GPIO inputs can be used to register interrupts from
external devices and to generate maskable
interrupts
Interrupt controller
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Maskable interrupts to Feroceon CPU core
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In endpoint mode, maskable interrupts to the
PCI/PCI Express interfaces
Timers
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Two general purpose 32-bit timer/counters
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One 32-bit Watchdog timer
Internal Architecture
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AHB bus for high-performance, low latency
Feroceon CPU core to DDR SDRAM connectivity
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Advanced Mbus architecture with any to any
concurrent I/O connectivity
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Dual port DDR SDRAM controller connectivity to
both AHB and Mbus
Bootable from
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Device interface
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PCI interface
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DDR interface
HSBGA, 23x23 mm, 388L package, 1 mm ball
pitch
Copyright © 2008 Marvell
April 29, 2008, Preliminary
Document Classification: Proprietary Information
Doc. No. MV-S103345-00 Rev. E
Page 5
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