19013 36th Ave. W, Suite H Lynnwood, WA 98036 USA
Manufacturer of High Quality Frequency Control Products
LV8845D LVDS Series
Low Voltage Differential Signal Output with Enable / Disable
6 Pad 7 x 5mm Leadless Surface Mount Oscillator
106.25 MHz and 212.5 MHz typically stock, other frequencies available
Consult factory for specific frequencies
Standard Specifications
Overall Frequency Stability
Operating Temperature Range
Operable Supply Voltage (Vcc)
High Level Output Voltage
Low Level Output Voltage
Differential Output Voltage
Differential Output Error
Offset Voltage
Offset Voltage Error
Output Leakage Current
Supply Current (Icc)
Symmetry (DC1)
Symmetry (DC2)
Rise and Fall Time (Tr & Tf)
RMS Jitter
Start Time
Enable / Disable Pin:
± 50 PPM, ± 25 PPM and ± 20 PPM over Operating Temp. Range
0 to +80°C is standard, can be extended to - 40 to +85°C
3.3 V ± 5%
1.43 V typical and 1.60 V maximum with output enabled (100 ohm load, R1 = 50 ohms) See Test circuit #6
0.90 V minimum and 1.10 V typical with output enabled (same conditions as above)
247 mV minimum, 330 mV typical and 454 mV maximum with output enabled (same conditions as above)
50 mV maximum with output enabled (same conditions as above)
1.125 V minimum, 1.25 V typical and 1.375 V maximum with output enabled (same as above)
50 mV maximum with output enabled (same as above)
100 uA maximum with output disabled
70 mA maximum
47/53% measured at crossing point
47/53% measured at 50% of output swing
1.5 nS max at 20% to 80% output swing (100 ohm load) See Test circuit #6 and Waveform #2
1.0 pS max at12 kHz to 20 MHz from the output
5.0 mS maximum
The Enable / Disable pin has an internal pull up and if the pin is not connected the oscilaltor is enabled. Pletronics strongly recommends
connecting the Enable / Disable pin to Vcc, if the oscillator is to be enabled at all times. In the disable condition, the output becomes a
high impedance and the internal oscillator circuit is inhibited (the internal circuit is stopped).
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Output Enable Time
Output Disable Time
2.0 V minimum at Enable / Disable Pin
0.8 V maximum at Enable / Disable Pin
±10
uA maximum at Enable / Disable
±50
uA maximum at Enable / Disable
200 nS maximum
200 nS maximum
Part Numbering Guide
Portions of the part number that appear after the frequency may not be marked on part (C of C provided)
Packaging
Tube or
16mm tape
8mm pitch
LV88 45 D V - 106.25M - XXX
(Internal Code or blank)
Model
Frequency Stability
45 = ± 50 PPM
44 = ± 25 PPM
20 = ± 20 PPM
Frequency in MHz
Special Specifications (choose all that apply)
E: Extended Operating Temp Range (-40 to +85
°
C) ,Optional
V: Supply Voltage of 3.3 volts
±5% (Required)
Consult factory for available frequencies and specs. Not all options available for all frequencies. A special part number may be assigned.
Frequency Stability is inclusive of frequency shifts due to calibration, temperature, supply voltage, shock, vibration and load
July 2004
Pl tronics, Inc.
(425) 776 -1880, Fax: (425) 776-2760, ple-sales@pletronics.com, www.pletronics.com
TBD
PECL, LVDS, OCXO
Page 1 - 7
Pl tronics, Inc.
.
Pl tronics, Inc.
.
19013 36th Ave. W, Suite H Lynnwood, WA 98036 USA
Manufacturer of High Quality Frequency Control Products
PECL and LVDS Layout Guidelines
SUGGESTED PCB LAYOUTS
Solder Pad Layout which
accommodates all PECL surface mount
devices
0.200 (5.08)
0 .185
(4.7)
0 .087
(2.2)
'B Pkg'
5 x7
TOP SIDE
BYPASS
BOTTOM
SIDE
BYPASS
0.055 0.100
(1.4) (2.54)
The output line should be designed with proper characteristic
impedance. Pletronics recommends laying out for the larger
'B package' with pads long enough to accept the smaller
5 x 7mm device. This permits the best option for alternate
sources of device. Pletronics also recommends connecting
Pin 1 and Pin 2 together on the models with
Q & QN OUT on pins 4 & 5. This allows
having E/D on either pin 1 or pin 2.
MULTI
LAYER
BYPASS
For Optimum Jitter Performance, Pletronics recommends:
A ground plane under the device with any other signals below the ground plane
Minimize other RF signals near device
No large transient signals (both current and voltage) should be routed under the device
Do not layout near a large magnetic field such as a high frequency switching power supply
Do not place near piezoelectric buzzers or mechancial fans
Reflow Cycle for lead free processing
250
Temperature
°
C
200
150
100
215°C
±
10°C
50 Seconds
175°C
±
10°C
120 to 160 Seconds
260°C max
10 Seconds max
T Rise= 4 Degree/second max
Mar 2004
Pl tronics, Inc.
(425) 776 -1880, Fax: (425) 776-2760, ple-sales@pletronics.com, www.pletronics.com
6
PECL, LVDS, OCXO
Page 1 - 7
Pl tronics, Inc.
.
19013 36th Ave. W, Suite H Lynnwood, WA 98036 USA
Manufacturer of High Quality Frequency Control Products
PECL and LVDS Layout Guidelines Continued
PECL Terminations:
Suggested Terminations for 50 ohm impedance matched termination
Vcc
Vcc
R1
Vcc
Out
Oscillator
GND
Vcc
Out
Oscillator
GND
Thevenin Equivalent Termination
Vcc
5.0 V
3.3 V
2.5 V
R1
82 ohm
130 ohm
249 ohm
R2
130 ohm
82 ohm
61.9 ohm
50 ohm
Vcc - 2.00 V
R2
Simple termination for NON impedance matched termination
Vcc
Vcc
Out
Oscillator
GND
R load
Vcc
5.0 V
3.3 V
2.5 V
R load
274 ohm
147 ohm
86.6 ohm
LVDS Terminations:
Vcc
Vcc
Q Out
Oscillator
GND QN Out
100 ohm
Design PCB traces for 50 ohm characteristic impedance
Mixed System Power Supply:
PECL
ECL
LVDS
To use multiple supply voltages requires level translation. Direct circuit connection is not valid.
Mixed supply voltages are allowed. No translation is necessary. (ECL is returned to the most positive
supply and this is common to all circuits)
Mixed supply voltages are allowed. LVDS signal levels are power supply independent.
3.3 V LVDS oscillators properly interface 2.5 V Logic Arrays for example.
Mar 2004
6A
Pl tronics, Inc.
(425) 776 -1880, Fax: (425) 776-2760, ple-sales@pletronics.com, www.pletronics.com
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