K4Y50164UC
K4Y50084UC
K4Y50044UC
K4Y50024UC
XDR
TM
DRAM
512Mbit XDR
TM
DRAM(C-die)
Revision 1.1
August 2006
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
XDR is a trademark of Rambus Inc.
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TM
DRAM
Change History
Revision
1.0
1.1
Month
December
August
Year
2005
2006
History
- First Copy
- Based on the Rambus XDR
TM
DRAM Datasheet Version 0.88
- Add comment on page 5
- Add T
MIN
on Table13, page 57
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TM
DRAM
0.0 Overview
The XDR DRAM device is a general-purpose high-performance memory device suitable for use in a broad range of applications,
including computer memory, graphics, video, and any other application where high bandwidth and low latency are required.
The 512Mb XDR DRAM device is a CMOS DRAM organized as 32M words by 16bits. The use of Differential Rambus Signaling
Level(DRSL) technology permits 4000/3200/2400 Mb/s transfer rates while using conventional system and board design technologies.
XDR DRAM devices are capable of sustained data transfers up to 8000 MB/s.
XDR DRAM device architecture allows the highest sustained bandwidth for multiple, interleaved randomly addressed memory transac-
tions. The highly-efficient protocol yields over 95% utilization while allowing fine access granuarity. The device’s eight banks support up
to four interleaved transactions.
1.0 Features
♦
Highest pin bandwidth available
- 4000/3200/2400 Mb/s Octal Data Rate(ODR) Signaling
♦
Bi-directional differential RSL(DRSL)
- Flexible read/write bandwidth allocation
- Minimum pin count
♦
On-chip termination
- Adaptive impedance matching
- Reduced system cost and routing complexity
♦
Highest sustained bandwidth per DRAM device
- Up to 8000 MB/s sustained data rate
- Eight banks : bank-interleaved transaction at full bandwidth
- Dynamic request scheduling
- Early-read-after-write support for maximum efficiency
- Zero overhead refresh
♦
Low Latency
- 2.0/2.5/3.33ns request packets
- Point-to-point data interconnect for fastest possible flight time
- Support for low-latency, fast-cycle cores
♦
Low Power
- 1.8V V
DD
- Programmable small-swing I/O signaling(DRSL)
- Low power PLL/DLL design
- Powerdown self-refresh support
- Per pin I/O powerdown for narrow-width operation
♦
0.49us refresh intervals(32K/16ms refresh)
♦
RoHS compliant
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TM
DRAM
2.0 Key Timing Parameters/Part Numbers
Organization
Bandwidth (1/t
BIT
)
a
2400
32Mx16
3200
4000
2400
64Mx8
3200
4000
2400
128Mx4
3200
4000
2400
256Mx2
3200
4000
Latency(t
RAC
)
b
36
35
28
36
35
28
36
35
28
36
35
28
Bin
c
A
B
C
A
B
C
A
B
C
A
B
C
Part Number
K4Y50164UC-JCA2
K4Y50164UC-JCB3
K4Y50164UC-JCC4
K4Y50084UC-JCA2
K4Y50084UC-JCB3
K4Y50084UC-JCC4
K4Y50044UC-JCA2
K4Y50044UC-JCB3
K4Y50044UC-JCC4
K4Y50024UC-JCA2
K4Y50024UC-JCB3
K4Y50024UC-JCC4
a.Data rate measured in Mbit/s per DQ differential pair. See “Timing Conditions” on page 58 and “ Timing Characteristics” on page 60.
Note that tBIT=t
CYCLE
/8
b.Read access time t
RAC
(= t
RCD-R
+t
CAC
) measured in ns. See “Timing Parameters” on page 61.
c.Timing parameter bin. See “Timing Parameters” on page 61. This is a measure of the number of interleaved read transactions needed
for maximum efficiency (the value Ceiling(t
RC-R
/t
RR-D
). For bin A, t
RC-R
/t
RR-D
=4, and for bin B, t
RC-R
/t
RR-D
=5 for bin C, t
RC-R
/t
RR-D
=6.
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TM
DRAM
3.0 General Description
The timing diagrams in Figure 1 illustrate XDR DRAM device write and read transactions. There are three sets of pins used for normal
memory access transactions: CFM/CFMN clock pins, RQ11..0 request pins, and DQ15..0/DQN15..0 data pins. The “N” appended to a
signal name denotes the complementary signal of a differential pair.
A transaction is a collection of packets needed to complete a memory access. A packet is a set of bit windows on the signals of a bus.
There are two buses that carry packets: the RQ bus and DQ bus. Each packet on the RQ bus uses a set of 2 bit-windows on each signal,
while the DQ bus uses a set of 16 bit-windows on each signal.
In the write transaction shown in Figure 1, a request packet (on the RQ bus) at clock edge T
0
contains an activate (ACT) command. This
causes row Ra of bank Ba in the memory component to be loaded into the sense amp array for the bank. A second request packet at
clock edge T
1
contains a write (WR) command. This causes the data packet D(a1) at edge T
4
to be written to column Ca1 of the sense
amp array for bank Ba. A third request packet at clock edge T
3
contains another write (WR) command. This causes the data packet
D(a2) at edge T
6
to also be written to column Ca2. A final request packet at clock edge T
13
contains a precharge (PRE) command.
The spacings between the request packets are constrained by the following timing parameters in the diagram: t
RCD-W
, t
CC
, and t
WRP
. In
addition, the spacing between the request packets and data packets is constrained by the t
CWD
parameter. The spacing of the CFM/
CFMN clock edges is constrained by t
CYCLE
.
Figure 1 : XDR DRAM Device Write and Read Transactions
T
0
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
8
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
CFM
CFMN
WR
RQ11..0 ACT WR
a0 a1
a2
t
RCD-W
t
CC
DQ15..0
t
CWD
DQN15..0
t
WRP
D(a1)
D(a2)
a0 = {Ba,Ra}
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
Write Transaction
T
0
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
8
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
CFM
CFMN
RQ11..0 ACT
a0
DQ15..0
DQN15..0
t
RCD-R
RD
a1
t
CC
RD
a2
t
RDP
PRE
a3
Q(a1)
Q(a2)
a2 = {Ba,Ca2}
a3 = {Ba}
Read Transaction
The read transaction shows a request packet at clock edge T
0
containing an ACT command. This causes row Ra of bank Ba of the mem-
ory component to load into the sense amp array for the bank. A second request packet at clock edge T
5
contains a read (RD) command.
This causes the data packet Q(a1) at edge T
11
to be read from column Ca1 of the sense amp array for bank Ba. A third request packet
at clock edge T
7
contains another RD command. This causes the data packet Q(a2) at edge T
13
to also be read from column Ca2. A final
request packet at clock edge T
10
contains a PRE command.
The spacings between the request packets are constrained by the following timing parameters in the diagram: t
RCD-R
, t
CC
, and t
RDP
. In
addition, the spacing between the request and data packets are constrained by the t
CAC
parameter.
* Any system or application incorporating random access memory products should be properly designed, tested and qualified to ensure
proper use or access of such memory products. Disproportionate, excessive and/or repeated access to a particular address or
addresses may result in reduction of product life.
t
CYCLE
PRE
a3
t
CYCLE
Transaction a: WR
t
CAC
Transaction a: RD
a0 = {Ba,Ra}
a1 = {Ba,Ca1}
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