based on 4Mx16 SDRAM with LVTTL, 4 banks & 4K Refresh
HYM76V4M655HG(L)T6 Series
D E S C R IP T IO N
The Hynix HYM76V4M655HG(L)T6 Series are 4Mx64bits Synchronous DRAM Modules. The modules are composed of four
4Mx16bits CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package on a 168pin
glass-epoxy printed circuit board. Two 0.33uF and one 0.1uF decoupling capacitors per each SDRAM are mounted on the PCB.
The Hynix HYM76V4M655HG(L)T6 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 32Mbytes
memory. The Hyundai HYM76V4M655HG(L)T6 Series are fully synchronous operation referenced to the positive edge of the clock . All
inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high
bandwidth.
FEATURES
•
•
•
•
PC100MHz support
168pin SDRAM Unbuffered DIMM
Serial Presence Detect with EEPROM
1.00” (25.40mm) Height PCB with double sided com-
ponents
Single 3.3±0.3V power supply
- 1, 2, 4 or 8 or Full page for Sequential Burst
•
•
All device pins are compatible with LVTTL interface
- 1, 2, 4 or 8 for Interleave Burst
Data mask function by DQM
•
Programmable CAS Latency ; 2, 3 Clocks
•
•
•
•
•
•
SDRAM internal banks : four banks
Module bank : one physical bank
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
O R D E R IN G IN F O R M A T IO N
Part No.
HYM76V4M655HGT6-8
HYM76V4M655HGT6-P
HYM76V4M655HGT6-S
HYM76V4M655HGLT6-8
HYM76V4M655HGLT6-P
HYM76V4M655HGLT6-S
Clock
Frequency
125MHz
100MHz
100MHz
Internal
Bank
Ref.
Power
SDRAM
Package
Plating
Normal
4 Banks
4K
Low Power
TSOP-II
Gold
125MHz
100MHz
100MHz
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of
circuits described. No patent licenses are implied.
Rev. 0.3/Apr.01
PC100 SDRAM S O D I M
M
H Y M 7 6 V 4 M 6 5 5 H G (L)T6 Seri
es
P IN D E S C R I T IO N
P
PIN
CK0, CK1
PIN NAME
Clock Inputs
D E S C R IPTION
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
Enables or disables all inputs except CK, CKE and DQM
Selects bank to be activated during /RAS activity
Selects bank to be read/written during /CAS activity
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
