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TM-056-CBF-A: 产品描述Integrated Timing Solution; 文件大小384KB，共8页; 制造商Vectron International, Inc.; 官网地址http://www.vectron.com/

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TM-056-CBF-A概述

Integrated Timing Solution

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TM-056

Integrated Timing Solution

The TM-056 is a compact Timing Module, which functions as a complete system clock solution for general Stratum 3 timing applications. The

TM-056 uses Vectron’s Digital and Analog Phase Locked Loop (DPLL and APLL) technology and can lock to 2 reference frequencies automatically.

The module has dual output clocks ranging from 8 kHz to 77.76 MHz. Simple control interface with comprehensive state engine, status and

alarm indications and fully automatic operation makes seamless system integration of the TM-056 module.

Features

• Single module Statum 3 synchronization solution.

• Complies with Telcordia GR-1244/GR-253 and ITU-T G.812/G.813

recommendations.

• Supports Free-run, Holdover and Lock modes.

• Accepts 2 reference inputs from frequency range 8kHz to 77.76MHz.

• Continuously monitors and evaluates both input reference signals

simultaneously.

• Provides two synchronized outputs with frequency range up to 77.76MHz.

• On board OCXO that provides excellent stability in Freerun and Holdover

mode.

• Loop filtering utilizing DPLL.

• Automatic “hit-less” switchover on loss of input.

• Holdover mode with 90 seconds of history.

• Alarms and status signals.

• Easy to use control interface and JTAG port for factory programming.

• Small dimensions 1.9” x 1.9” x 0.55”.

• Product is compliant to RoHS directive and fully compatible with lead free

assembly.

Applications

•

Multi-service Switches and Routers

ATM

Gateway

Access

EDGE

Core

SONET

SDH

DWDM

Block Diagram

OCXO

EX REF 1

EX REF 2

Reference

Monitor

and

Selection

DPLL

APLL

Output

Dividers

OUT 1

OUT 2

CNT 1

CNT 2

CPU

HOLDOVER

REF 1

REF 2

FREERUN

ALARM

UNLOCK

Vectron International • 267 Lowell Road Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com

Road, Hudson

Description

The TM-056 is based on a digital PLL (DPLL) that performs filtering of input signals, and is complemented by an analog PLL (APLL) required to

deliver high quality output signals. The most critical element of the TM-056 is the DPLL that generates a phase-locked clock, filters jitter and

wander and suppresses input phase transients. All of these features are in agreement with international standards. The DPLL supports three

mandatory modes of operation. (Free-run, Lock and Holdover). Each of these modes places specific requirements on the building blocks of the

DPLL.

In Free-run mode the output is locked to an internal OCXO, and therefore timing and synchronization signals are based on the accuracy of

on-board oscillators. This mode is typically used when a master clock source is required, not valid history of data for the Holdover mode, or

immediately following system power-up before network synchronization is achieved.

In Holdover mode, the TM-056 generates a clock based on data collected from past reference signals when the module was locked. The

Holdover mode is typically used when no external reference is available. The stability of the output signal in Holdover mode depends of the

stability of the on-board oscillator. By default the TM-056 uses an OCXO as an on-board oscillator, but other type of oscillators are available on

request.

In Lock mode the device can be locked to one of two external reference signals. The Lock mode is typically used when a slave clock source

synchronized to the network is required. In this mode the TM-056 provides timing signals which are synchronized to one of two reference inputs

(i.e. REF1 or REF2). The input reference signals may have a variety of nominal frequencies, which are specified by customers.

Both input references are continuously monitored and evaluated by the module in terms of presence and frequency offset relative to the local

oscillator. The TM-056 rejects all reference signals that are out of the frequency range of approximately ±17ppm. A reference will be qualified if

the signal is present and within the frequency limit for more than approximately 20s.

The TM-056 dynamically changes the loop bandwidth according to the status of the DPLL. There are three stages for the DPLL to be locked. The

first stage is frequency acquisition that runs until the frequency becomes equal to the reference. The second stage is phase acquisition that runs

until a new phase reference is determined. The third stage is tracking when the DPLL is locked and tracks the phase reference with very low loop

bandwidth. This method with three stages ensures a minimum locking time and minimum phase jumps and shifts during rearrangement.

The phase data is continuously collected for the history buffer during the time when the unit is locked to any of the input references. The history

buffer is actually a circular buffer in memory that keeps valid phase data for Holdover mode for the last 90 seconds of operation. When the

TM-056 enters Holdover mode the data from the buffer is validated and further processed. At the beginning of operation the unit has no valid

history buffer.

The APLL is locked to DPLL output and provides low jitter output. The TM-056 module provides two output signals OUT1 and OUT2. The outputs

are generated by APLL and scaled by the output dividers. The frequency of the APLL oscillator is specified according to an application where the

TM-056 will be used.

The J-TAG service port is used for on board chip programming and debugging purposes during production and testing. The port is for factory

use only and any unauthorized access can damage the unit.

The TM-056 provides a detailed monitoring and indications of operation mode and status of the unit. There are six digital outputs that report

statuses and alarms of the module. These alarms are mainly used for communication between the module and equipment where the module is

operating.

Status Indications

HOLDOVER

REF 1

REF 2

FREE-RUN

UNLOCK

ALARM

Mode of Operation

The signal is ON (logic high) when TM-056 in Holdover mode.

The signal is ON (logic high) when TM-056 in Lock mode using EX REF 1.

The signal is ON (logic high) when TM-056 in Lock mode using EX REF 2.

The signal is ON (logic high) when TM-056 in Free-run mode.

The signal in ON (logic high) when TM-056 is not locked to an external reference.

The signal is ON (logic high) when TM-056 is in Holdover of Free-run mode.

A simple control interface is

available for user to control the

operation of the TM-056. The two

external inputs CNT1 and CNT2

provide this feature. The truth

table below shows behavior of the

TM-056 module according to the

control inputs states.

TM-056 Status Indications

CNT2

CNT1

Mode of Operation

Free-run

Locked to EX REF1

Locked to EX REF2

Holdover

By changing the control inputs the user can change the state of the TM-056 accord-

ing to the state engine diagram. The state engine diagram of the TM-056 shows

the transients between the three operating modes: Free-run, Lock and Holdover,

shown as an ellipse, in a changing environment. The temporary operating states,

showed as a circle, are used internally until one of the three modes is reached. Be-

sides the control inputs (CNT1 and CNT2), certain types of inputs and statuses affect

the changes in the state engine such as the availability of external references and

change of the quality of the input reference signal otside predefined limits.

TM-056 Mode selection

Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com

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TM-056-CBF-A

TM-056-CBF-A概述

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