INTEGRATED CIRCUITS
DATA SHEET
SAA7185
Digital Video Encoder (DENC2)
Preliminary specification
Supersedes data of 1995 Jun 15
File under Integrated Circuits, IC02
1996 Jul 08
Philips Semiconductors
Preliminary specification
Digital Video Encoder (DENC2)
FEATURES
•
CMOS 5 V device
•
Digital PAL/NTSC encoder
•
System pixel frequency 13.5 MHz
•
Accepts MPEG decoded data
•
8-bit wide MPEG port
•
Input data format Cb, Y, Cr etc. (CCIR 656)
•
16-bit wide YUV input port
•
I
2
C-bus control or alternatively MPU parallel control port
•
Encoder can be master or slave
•
Programmable horizontal and vertical input
synchronization phase
•
Programmable horizontal sync output phase
•
OSD overlay with Look-Up Tables (LUTs) 8
×
3 bytes
•
Colour bar generator
•
Line 21 Closed Caption encoder
•
Cross-colour reduction
•
DACs operating at 27 MHz with 10-bit resolution
•
Controlled rise/fall times of output syncs and blanking
•
Down-mode of DACs
•
CVBS and S-Video output simultaneously
•
PLCC68 package.
QUICK REFERENCE DATA
SYMBOL
V
DDA
V
DDD
I
DDA
I
DDD
V
i
V
o(p-p)
R
L
ILE
DLE
T
amb
analog supply voltage
digital supply voltage
analog supply current
digital supply current
input signal voltage levels
analog output signal voltages Y, C and CVBS without load
−
(peak-to-peak value)
load resistance
LF integral linearity error
LF differential linearity error
operating ambient temperature
80
−
−
0
PARAMETER
MIN.
4.75
4.5
−
−
TYP.
5.0
5.0
50
140
2
−
−
−
−
GENERAL DESCRIPTION
SAA7185
The SAA7185 encodes digital YUV video data to an
NTSC, PAL CVBS or S-Video signal.
The circuit accepts CCIR compatible YUV data with
720 active pixels per line in 4 : 2 : 2 multiplexed formats,
for example MPEG decoded data. It includes a sync/clock
generator and on-chip Digital-to-Analog Converters
(DACs).
The circuit is compatible to the DIG-TV2 chip family.
MAX.
5.25
5.5
55
170
−
−
±2
±1
+70
V
V
UNIT
mA
mA
V
Ω
LSB
LSB
°C
TTL compatible
1996 Jul 08
2
Philips Semiconductors
Preliminary specification
Digital Video Encoder (DENC2)
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
SAA7185WP
BLOCK DIAGRAM
PLCC68
DESCRIPTION
plastic leaded chip carrier; 68 leads
SAA7185
VERSION
SOT188-2
KEY
SEL_ED
18
MP7
to MP0
VP0
to VP7
20 to 27
8
9 to 16
8
OSD0
to OSD2
32 to 34
VDDD1
RTCI
43
to VDDD3
17,37,67
VDDA1
to
VrefH VDDA4
II
47 55 48,50,
54,56
53
A
51
D
49
52
46
31
DATA
MANAGER
ENCODER
OUTPUT
INTERFACE
CVBS
Y
CHROMA
VSSA
VrefL
8
8
internal control bus
8
RCM1
RCM2
29
8
30
8
clock timing signals
8
SAA7185
CONTROL
INTERFACE
SYNC
CLK
1,8,19
28,35,
42,62
63 to 66
2 to 5
68
61
CS/SA
59
60
58
57
41
XTALI
40
38
LLC
39
36
6
7
MBE733
VSSD1
to
VSSD7
DP0
to DP7
A0/SDA
RESET
CDIR
Cref
RCV2
SEL_MPU
RW/SCL
DTACK
XTALO
RCV1
Fig.1 Block diagram.
1996 Jul 08
andbook, full pagewidth
3
Philips Semiconductors
Preliminary specification
Digital Video Encoder (DENC2)
PINNING
SYMBOL
V
SSD1
DP4
DP5
DP6
DP7
RCV1
RCV2
V
SSD2
VP0
VP1
VP2
VP3
VP4
VP5
VP6
VP7
V
DDD1
SEL_ED
V
SSD3
MP7
MP6
MP5
MP4
MP3
MP2
MP1
MP0
V
SSD4
RCM1
RCM2
KEY
OSD0
OSD1
OSD2
V
SSD5
CDIR
V
DDD2
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
digital ground 5
On-Screen Display data. This is the index for the internal OSD look-up table.
digital ground 4
Raster Control 1 for MPEG port. This pin provides a VS/FS/FSEQ signal.
MPEG Port. It is an input for CCIR 656 style multiplexed YUV data.
digital supply voltage 1
digital ground 1
DESCRIPTION
SAA7185
Upper 4 bits of the Data Port. If pin 68 (SEL_MPU) is HIGH, this is the data bus of the parallel
MPU interface. If it is LOW, they are the UV lines of the Video Port.
Raster Control 1 for Video port. Depending on the synchronization mode, this pin
receives/provides a VS/FS/FSEQ signal.
Raster Control 2 for Video port. Depending on the synchronization mode, this pin
receives/provides an HS/HREF/CBL signal.
digital ground 2
Video Port. This is an input for CCIR 656 compatible, multiplexed video data. If the 16-bit
DIG-TV2 format is used, this is the Y data.
Select Encoder Data. Selects data either from MPEG port or from video port as encoder input.
digital ground 3
Raster Control 2 for MPEG port. This pin provides an HS pulse for the MPEG decoder.
Key signal for OSD. It is active HIGH.
Clock direction. If the CDIR input is HIGH, the circuit receives a clock signal, otherwise LLC
and CREF are generated by the internal crystal oscillator.
digital supply voltage 2
1996 Jul 08
4
Philips Semiconductors
Preliminary specification
Digital Video Encoder (DENC2)
SAA7185
SYMBOL
LLC
C
ref
XTALO
XTALI
V
SSD6
RTCI
AP
SP
V
refL
V
refH
V
DDA1
CHROMA
V
DDA2
Y
V
SSA
CVBS
V
DDA3
I
I
V
DDA4
RESET
DTACK
RW/SCL
A0/SDA
CS/SA
V
SSD7
DP0
DP1
DP2
DP3
V
DDD3
SEL_MPU
PIN
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
digital supply voltage 3
DESCRIPTION
Line-Locked Clock. This is the 27 MHz master clock for the encoder. The direction is set by
the CDIR pin.
Clock Reference signal. This is the clock qualifier for DIG-TV2 compatible signals.
Crystal oscillator output (to crystal).
Crystal oscillator input (from crystal). If the oscillator is not used, this pin should br connected
to ground.
digital ground 6
Real Time Control Input. If the clock is provided by an SAA7151B, RTCI should be connected
to the RTCO pin of the decoder to improve the signal quality.
Test pin. Connect to digital ground for normal operation.
Test pin. Connect to digital ground for normal operation.
Lower reference voltage input for the DACs.
Upper reference voltage input for the DACs.
Analog positive supply voltage 1 for the DACs and output amplifiers.
Analog output of the chrominance signal.
Analog supply voltage 2 for the DACs and output amplifiers.
Analog output of the luminance signal.
Analog ground for the DACs and output amplifiers.
Analog output of the CVBS signal.
Analog supply voltage 3 for the DACs and output amplifiers.
Current input for the output amplifiers, connect via a 15 kΩ resistor to V
DDA
.
Analog supply voltage 4 for the DACs and output amplifiers.
Reset input, active LOW. After reset is applied, all outputs are in 3-state input mode.
The I
2
C-bus receiver waits for the start condition.
Data acknowledge output of the parallel MPU interface, active LOW, otherwise high
impedance.
If pin 68 (SEL_MPU) is HIGH, this is the read/write signal of the parallel MPU interface,
otherwise it is the I
2
C-bus serial clock input.
If pin 68 (SEL_MPU) is HIGH, this is the address signal of the parallel MPU interface,
otherwise it is the I
2
C-bus serial data input/output.
If pin 68 (SEL_MPU) is HIGH, this is the chip select signal of the parallel MPU interface,
otherwise it is the I
2
C-bus slave address select pin. LOW: slave address = 88H, HIGH = 8CH.
digital ground 7
Lower 4 bits of the Data Port. If pin 68 (SEL_MPU) is HIGH, this is the data bus of the parallel
MPU interface. If it is LOW, they are the UV lines of the Video Port.
Select MPU interface input. If it is HIGH, the parallel MPU interface is active, otherwise the
I
2
C-bus interface will be used.
1996 Jul 08
5
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