INTEGRATED CIRCUITS
DATA SHEET
SAA7128H; SAA7129H
Digital video encoder
Product specification
File under Integrated Circuits, IC22
2000 Mar 08
Philips Semiconductors
Product specification
Digital video encoder
CONTENTS
1
2
3
4
5
6
7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
8
8.1
8.2
9
9.1
10
11
11.1
11.2
11.3
11.4
11.5
12
13
14
FEATURES
GENERAL DESCRIPTION
ORDERING INFORMATION
QUICK REFERENCE DATA
BLOCK DIAGRAM
PINNING
FUNCTIONAL DESCRIPTION
Versatile fader
Data manager
Encoder
RGB processor
SECAM processor
Output interface/DACs
Synchronization
Clock
I
2
C-bus interface
Input levels and formats
Bit allocation map
I
2
C-bus format
Slave receiver
Slave transmitter
CHARACTERISTICS
Explanation of RTCI data bits
Teletext timing
APPLICATION INFORMATION
Analog output voltages
PACKAGE OUTLINE
SOLDERING
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
Suitability of surface mount IC packages for
wave and reflow soldering methods
DEFINITIONS
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I
2
C COMPONENTS
SAA7128H; SAA7129H
2000 Mar 08
2
Philips Semiconductors
Product specification
Digital video encoder
1
FEATURES
SAA7128H; SAA7129H
•
Monolithic CMOS 3.3 V device, 5 V I
2
C-bus optional
•
Digital PAL/NTSC/SECAM encoder
•
System pixel frequency 13.5 MHz
•
54 MHz double-speed multiplexed D1 interface capable
of splitting data into two separate channels (encoded
and baseband)
•
Three Digital-to-Analog Converters (DACs) for CVBS
(CSYNC), VBS (CVBS) and C (CVBS) two times
oversampled with 10-bit resolution (signals in brackets
optional)
•
Three DACs for RED (C
R
), GREEN (Y) and BLUE (C
B
)
two times oversampled with 9-bit resolution (signals in
brackets optional)
•
Alternatively, an advanced composite sync is available
on the CVBS output for RGB display centring
•
Real-time control of subcarrier
•
Cross-colour reduction filter
•
Closed captioning encoding and World Standard
Teletext (WST) and North-American Broadcast Text
System (NABTS) teletext encoding including sequencer
and filter
•
Copy Generation Management System (CGMS)
encoding (CGMS described by standard CPR-1204 of
EIAJ); 20 bits in lines 20/283 (NTSC) can be loaded via
I
2
C-bus
•
Fast I
2
C-bus control port (400 kHz)
•
Line 23 Wide Screen Signalling (WSS) encoding
•
Video Programming System (VPS) data encoding in
line 16 (50/625 lines counting)
•
Encoder can be master or slave
•
Programmable horizontal and vertical input
synchronization phase
•
Programmable horizontal sync output phase
3
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
SAA7128H
SAA7129H
QFP44
DESCRIPTION
plastic quad flat package; 44 leads (lead length 1.3 mm); body
10
×
10
×
1.75 mm
VERSION
SOT307-2
•
Internal Colour Bar Generator (CBG)
•
Macrovision Pay-per-View copy protection system
rev. 7.01 and rev. 6.1 as option; this applies to
SAA7128H only. The device is protected by USA patent
numbers 4631603, 4577216 and 4819098 and other
intellectual property rights. Use of the macrovision
anti-copy process in the device is licensed for
non-commercial home use only. Reverse engineering or
disassembly is prohibited. Please contact your nearest
Philips Semiconductors sales office for more information
•
Controlled rise/fall times of output syncs and blanking
•
On-chip crystal oscillator (3rd-harmonic or fundamental
crystal)
•
Down mode (low output voltage) or power-save mode of
DACs
•
QFP44 package.
2
GENERAL DESCRIPTION
The SAA7128H; SAA7129H encodes digital C
B
-Y-C
R
video data to an NTSC, PAL or SECAM CVBS or S-video
signal. Simultaneously, RGB or bypassed but interpolated
C
B
-Y-C
R
signals are available via three additional DACs.
The circuit at a 54 MHz multiplexed digital D1 input port
accepts two ITU-R BT.656 compatible C
B
-Y-C
R
data
streams with 720 active pixels per line in
4 : 2 : 2 multiplexed formats, for example MPEG decoded
data with overlay and MPEG decoded data without
overlay, whereas one data stream is latched at the rising,
the other one at the falling clock edge.
It includes a sync/clock generator and on-chip DACs.
2000 Mar 08
3
Philips Semiconductors
Product specification
Digital video encoder
4
QUICK REFERENCE DATA
SYMBOL
V
DDA
V
DDD
I
DDA
I
DDD
V
i
V
o(p-p)
R
L
LE
lf(i)
LE
lf(d)
T
amb
analog supply voltage
digital supply voltage
analog supply current
digital supply current
input signal voltage levels
analog output signal voltages Y, C and CVBS without load
(peak-to-peak value)
load resistance
low frequency integral linearity error
low frequency differential linearity error
ambient temperature
PARAMETER
SAA7128H; SAA7129H
MIN.
3.15
3.0
−
−
1.25
75
−
−
0
TYP.
3.3
3.3
130
75
1.35
−
−
−
−
MAX.
3.45
3.6
150
100
1.50
300
±3
±1
70
UNIT
V
V
mA
mA
V
Ω
LSB
LSB
°C
TTL compatible
2000 Mar 08
4
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2000 Mar 08
RESET SDA
40
VDD(I2C)
SA
20
21
I
2
C-BUS
INTERFACE
42
SCL
41
35
5
Philips Semiconductors
Digital video encoder
BLOCK DIAGRAM
XTALI XTALO RCV1 RCV2 TTXRQ XCLK
34
7
8
43
37
LLC1
4
VDDA1 VDDA3
VDDA2 VDDA4
25
28
31
36
SAA7128H
SAA7129H
clock and timing
I
2
C-bus control
SYNC/CLOCK
I
2
C-bus control
I
2
C-bus control
I
2
C-bus control
30
D
OUTPUT
INTERFACE
A
27
24
22
CVBS
(CSYNC)
VBS
(CVBS)
C
(CVBS)
VSSA1
VSSA2
VSSA3
RED
GREEN
BLUE
MP7 to MP0
9 to 16 MPpos
SWITCH
MPneg
MPA
MP
FADER
Y
ENCODER
CbCr
Y
MPB
VP
C
5
I
2
C-bus
TTX
44
control
I
2
C-bus
control
Y
RGB
PROCESSOR
CbCr
A
32
I
2
C-bus control
33
23
26
29
D
5
18
38
6
17
39
2
3
19
MHB572
SAA7128H; SAA7129H
VSSD1 VSSD2 VSSD3 VDDD1 VDDD2 VDDD3
SP
AP
RTCI
Product specification
Fig.1 Block diagram.
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