2.5 GHz, Any Differential In-to-LVPECL, Programmable Clock
Divider/Fanout Buffer with Internal Termination
Features
• Integrated Programmable Clock Divider and 1:2
Fanout Buffer
• Guaranteed AC Performance over Temperature
and Voltage:
- >2.5 GHz f
MAX
- <250 ps t
r
/t
f
- <15 ps Within-Device Skew
• Low Jitter Design:
- <10 ps
PP
Total Jitter
- <1 ps
RMS
Cycle-to-Cycle Jitter
• Unique Input Termination and V
T
Pin for
DC-Coupled and AC-Coupled Inputs; CML,
PECL, LVDS, and HSTL
• TTL/CMOS Inputs for Select and Reset
• 100KEP-Compatible LVPECL Outputs
• Parallel Programming Capability
• Programmable Divider Ratios of 1, 2, 4, 8, and 16
• Low-Voltage Operation: 2.5V or 3.3V
• Output Disable Function
• –40°C to +85°C Temperature Range
• Available in 16-Pin (3 mm x 3 mm) QFN Package
General Description
This low-skew, low-jitter device is capable of accepting
a high-speed (e.g., 622 MHz or higher) CML, LVPECL,
LVDS, or HSTL clock input signal and dividing down the
frequency using a programmable divider ratio to create
a frequency-locked, lower speed version of the input
clock. Available divider ratios are 2, 4, 8, and 16, or
straight pass-through. In a typical 622 MHz clock
system this would provide availability of 311 MHz,
155 MHz, 77 MHz, or 38 MHz auxiliary clock
components.
The differential input buffer has a unique internal
termination design that allows access to the
termination network through a V
T
pin. This feature
allows the device to easily interface to different logic
standards. A V
REF-AC
reference is included for
AC-coupled applications.
The /RESET input asynchronously resets the divider. In
the pass-through function (divide by 1) the /RESET
synchronously enables or disables the outputs on the
next falling edge of IN (rising edge of /IN).
Package Type
SY89874U
3 mm x 3 mm QFN-16 (M)
(Top View)
VCC
14
Applications
• SONET/SDH Line Cards
• Transponders
• High-End Multiprocessor Sensors
16
15
13
12
11
10
9
GND
S0
S1
Q0
/Q0
Q1
/Q1
1
2
3
4
5
6
7
8
IN
VT
VREF-AC
/IN
United States Patent No. RE44,134
2018 Microchip Technology Inc.
/RESET
NC
S2
VCC
DS20006108A-page 1
SY89874U
Functional Block Diagram
S2
/RESET
ENABLE
FF
ENABLE
MUX
MUX
Q0
/Q0
IN
R0
V
T
R1
/IN
S0
DECODER
S1
DIVIDED
BY
2, 4, 8
or 16
Q1
/Q1
V
REF-AC
Typical Performance
OC-12 to OC-3
Translator/Divider
LVDS
622MHz
CLOCK-IN
DIVIDE-BY-4
LVPECL
155.5MHz
CLOCK-OUT
622MHz In
IN
/IN
Q0
155.5MHz Out
/Q0
TRUTH TABLE
/RESET
1
1
1
1
1
0
S2
0
1
1
1
1
1
S1
X
0
0
1
1
X
S0
X
0
1
0
1
X
Outputs
Reference clock (pass-through)
Reference clock ÷ 2
Reference clock ÷ 4
Reference clock ÷ 8
Reference clock ÷ 16
Q = Low, /Q = High clock disable
DS20006108A-page 2
2018 Microchip Technology Inc.
SY89874U
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Supply Voltage (V
CC
) ................................................................................................................................ –0.5V to +4.0V
Input Voltage (V
IN
) ............................................................................................................................–0.5V to V
CC
+ 0.3V
ECL Output Current
Continuous ...................................................................................................................................................50 mA
Surge .........................................................................................................................................................100 mA
Input Current IN, /IN (I
IN
)....................................................................................................................................... ±50 mA
V
T
Current (I
VT
) ................................................................................................................................................... ±100 mA
V
REF-AC
Sink/Source Current (I
VREF-AC
) (Note
1)
.................................................................................................. ±2 mA
Operating Ratings ††
Supply Voltage (V
CC
) ..............................................................................................................+3.3V ±10% or +2.5V ±5%
† Notice:
Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only
and functional operation is not implied at conditions other than those detailed in the operational sections of this data
sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
†† Notice:
The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
Note 1:
Due to the limited drive capability, use for input of the same package only.
2018 Microchip Technology Inc.
DS20006108A-page 3
SY89874U
DC ELECTRICAL CHARACTERISTICS (Note
1)
Electrical Characteristics:
T
A
= –40°C to +85°C, unless otherwise stated.
Parameters
Power Supply
Power Supply Current
Differential Input
Resistance (IN-to-/IN)
Input High Voltage
(IN, /IN)
Input Low Voltage (IN, /IN)
Input Voltage Swing
Different Input Voltage
Swing
Input Current (IN, /IN)
Reference Voltage
Note 1:
2:
Sym.
V
CC
I
CC
R
IN
V
IH
V
IL
V
IN
V
DIFF_IN
I
IN
V
REF-AC
Min.
2.375
—
90
0.1
–0.3
0.1
0.2
—
V
CC
–
1.525
Typ.
—
50
100
—
—
—
—
—
V
CC
–
1.425
Max.
3.63
75
110
V
CC
+ 0.3
V
IH
– 0.1
V
CC
—
45
V
CC
–
1.325
Units
V
mA
Ω
V
V
V
V
mA
V
—
No load, max. V
CC
—
Note 2
Note 2
Note 2, Note 3
Note 2, Note 3, Note 4
Note 2
Note 5
Conditions
3:
4:
5:
The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium
has been established.
Due to the internal termination (see
Input Buffer Structure),
the input current depends on the applied volt-
ages at IN, /IN, and V
T
inputs. Do not apply a combination of voltages that causes the input current to
exceed the maximum limit. Performance might be impacted if the differential inputs are driven sin-
gle-ended.
See
Timing Diagram
for V
IN
definition. V
IN
(maximum) is specified when V
IN
is floating.
See
Definition of Single-Ended and Differential Swing
section for V
DIFF
definition.
Operating using V
REF-AC
is limited to AC-coupled PECL or CML applications only. Connect directly to the
V
T
pin.
LVPECL (100KEP) DC ELECTRICAL CHARACTERISTICS
Electrical Characteristics:
V
CC
= 3.3V ±10% or 2.5V ±5%; T
A
= –40°C to +85°C, R
L
= 50Ω to V
CC
– 2V, unless
otherwise stated.
Note 1
Parameter
Output High Voltage
Output Low Voltage
Output Voltage Swing
Differential Output
Voltage Swing
Note 1:
Symbol
V
OH
V
OL
V
OUT
V
DIFF_OUT
Min.
V
CC
– 1.145
V
CC
– 1.945
550
1.10
Typ.
V
CC
– 1.020
V
CC
– 1.820
800
1.60
Max.
V
CC
–
0.895
V
CC
–
1.695
1050
2.10
Units
V
V
mV
V
—
—
—
—
Condition
The circuit is designed to meet the DC specifications shown in the LVPECL (100KEP) Electrical Charac-
teristics table after thermal equilibrium has been established.
DS20006108A-page 4
2018 Microchip Technology Inc.
SY89874U
LVTTL/CMOS DC ELECTRICAL CHARACTERISTICS
Electrical Characteristics:
V
CC
= 3.3V ±10% or 2.5V ±5%; T
A
= –40°C to +85°C, unless otherwise stated.
Note 1
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Note 1:
Symbol
V
IH
V
IL
I
IH
I
IL
Min.
2.0
—
–125
–300
Typ.
—
—
—
—
Max.
—
0.8
20
—
Units
V
V
µA
µA
—
—
—
—
Condition
The circuit is designed to meet the DC specifications shown in the LVTTL/CMOS Electrical Characteristics
table after thermal equilibrium has been established.
AC ELECTRICAL CHARACTERISTICS
Electrical Characteristics:
V
CC
= 3.3V ±10% or 2.5V ±5%; T
A
= –40°C to +85°C, R
L
= 50Ω to V
CC
– 2V, unless
otherwise stated.
Note 1, Note 2
Parameter
Maximum Output Toggle
Frequency
Maximum Input Frequency
Differential Propagation
Delay IN-to-Q
Within Device Skew
(Differential) Q0 - Q1
Part-to-Part Skew
(Differential)
Reset Recovery Time
Cycle-to-Cycle Jitter
Total Jitter
t
JITTER
Additive Phase Jitter
Rise/Fall Time (20% to
80%)
Note 1:
2:
3:
4:
5:
6:
t
r
/t
f
—
70
81
150
—
250
t
PD
Symbol
f
MAX
Min.
2.5
3.2
540
480
—
t
SKEW
—
t
RR
600
—
—
—
—
—
—
250
—
1
10
ps
ps
PP
Note 4
Note 6
Typ.
—
—
650
600
7
Max.
—
—
790
730
15
ps
Note 3
ps
Units
GHz
Condition
Output swing
≥400
mV
Divide by 2, 4, 8, 16
Input swing <400 mV
Input swing
≥400
mV
ps
RMS
Note 5
Integration Range: 12 kHz to
ps
RMS
20 MHz, Carrier: 622.08 MHz,
T
A
= +25°C
ps
—
Measured with 400 mV signal, 50% duty cycle, all outputs loaded with 50Ω to V
CC
– 2V, unless otherwise
stated.
Specification for packaged product only.
Skew is measured between outputs under identical transitions.
See the
Timing Diagram
section.
Cycle-to-cycle jitter definition: The variation in period between adjacent cycles over a random sample of
adjacent cycle pairs. t
JITTER_CC
= t
n
– t
n+1
, where “t” is the time between rising edges of the output signal.
Total jitter definition: With an ideal clock input, of frequency
≤f
MAX
(device), no more than one output edge
in 10
12
output edges will deviate by more than the specified peak-to-peak jitter value.
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