Micrel, Inc.
PRECISION 1:8 LVPECL FANOUT
BUFFER WITH 2:1 RUNT PULSE
ELIMINATOR INPUT MUX
Precision Edge
®
SY89837U
Precision Edge
®
SY89837U
FEATURES
■
Selects between two clocks, and provides 8
precision, low skew LVPECL output copies
■
Guaranteed AC performance over temperature and
supply voltage:
■
Wide operating frequency: 1kHz to >1.5GHz
• <975ps in-to-out t
pd
• <180ps t
r
/t
f
• <40ps output-to-output skew
■
Unique input isolation design minimizes crosstalk
■
Ultra-low jitter design:
• 150fs RMS phase jitter
• <0.7ps
rms
MUX crosstalk induced jitter
Precision Edge
®
DESCRIPTION
The SY89837U is a low jitter, low skew, high-speed 1:8
fanout buffer with a unique, 2:1 differential input multiplexer
(MUX) optimized for clock redundant switchover applications.
Unlike standard multiplexers, the SY89837U unique 2:1 runt
pulse eliminator (RPE) input MUX prevents any short cycles
or “runt” pulses during switchover. In addition, a unique
fail-safe input protection prevents metastable conditions
when the selected input clock fails to a static DC differential
voltage (differential input voltage drops below 200mV).
The SY89837U distributes clock frequencies from 1kHz to
1.5GHz, guaranteed, over temperature and voltage.
The differential input includes Micrel’s unique, 3-pin input
termination architecture that allows customers to interface
to any differential signal (AC- or DC-coupled) as small as
200mV without any level shifting or termination resistor
networks in the signal path. The outputs are 800mV, 100k
compatible LVPECL with fast rise/fall times guaranteed to
be less than 200ps.
The SY89837U operates from a +2.5V ±5% or +3.3V ±10%
supply and is guaranteed over the full industrial temperature
range of –40°C to +85°C. The SY89837U is part of Micrel’s
high-speed, Precision Edge
®
product line.
All support documentation can be found on Micrel’s web
site at: www.micrel.com.
■
Unique input termination and VT pin accepts DC- or
AC-coupled inputs (CML, PECL, LVDS)
■
800mV LVPECL output swing
■
Power supply +2.5V ±5% or +3.3V ±10%
■
–40°C to +85°C industrial temperature range
■
Available in 32-pin (5mm x 5mm) QFN package
APPLICATIONS
■
Redundant clock distribution
■
Fail-safe clock protection
United States Patent No. RE44,134
Precision Edge is a registered trademark of Micrel, Inc.
M9999-060410
hbwhelp@micrel.com or (408) 955-1690
Rev.: F
Amendment: /0
1
Issue Date: June 2010
Micrel, Inc.
Precision Edge
®
SY89837U
TYPICAL APPLICATIONS CIRCUIT
Figure 1. Simplified Example Illustrating Runt Pulse Eliminator (RPE)
Circuit When Primary Clock Fails
TRUTH TABLE
Inputs
IN0
0
1
X
X
/IN0
1
0
X
X
IN1
X
X
0
1
/IN1
X
X
1
0
SEL
0
0
1
1
Outputs
Q
0
1
0
1
/Q
1
0
1
0
M9999-060410
hbwhelp@micrel.com or (408) 955-1690
2
Micrel, Inc.
Precision Edge
®
SY89837U
PACKAGE/ORDERING INFORMATION
Ordering Information
(1)
Part Number
SY89837UMG
SY89837UMGTR
(2)
Package
Type
QFN-32
QFN-32
Operating
Range
Industrial
Industrial
Package
Marking
Lead
Finish
SY89837U with
Pb-Free
Pb-Free bar-line indicator NiduAu
SY89837U with
Pb-Free
Pb-Free bar-line indicator NiduAu
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A
= 25°C, DC Electricals only.
2. Tape and Reel.
32-Pin QFN
PIN DESCRIPTION
Pin Number
1, 3,
6, 8
2, 7
Pin Name
IN0, /IN0,
IN1, /IN1
VT0, VT1
Pin Function
Differential Inputs: These input pairs are the differential signal inputs to the device. These inputs
accept AC- or DC-coupled signals as small as 200mV. Each pin of a pair internally terminates to
a VT pin through
50Ω.
Please refer to the “Input Interface Applications” section for more details.
Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The
VT0 and VT1 pins provide a center-tap to a termination network for maximum interface
flexibility.
See the “Input Interface Applications” section for more details.
This single-ended TTL/CMOS-compatible input selects the inputs to the multiplexer. This input
is internally connected to a
25kΩ
pull-up resistor and will default to a logic HIGH state if left open.
Positive power supply. Bypass with
possible.
low ESR capacitors as close to the pins as
31
9, 19, 22, 32
30, 28, 26, 24,
18, 16, 14, 12,
29, 27, 25, 23,
17, 15, 13, 11
20,21
10
SEL
VCC
Q0 – Q7,
/Q0 – /Q7
Differential Outputs: These LVPECL output pairs are the outputs of the device. They are a logic
function of the IN0, IN1, and SEL inputs. Please refer to the truth table for details. Unused
output pairs may be left open.
Ground. Ground and exposed pad to be tied together to most negative potential of chip.
Power-On Reset (POR) Initialization Capacitor. When using the multiplexer with RPE capability,
this pin is tied to a capacitor to V
CC
. The purpose is to ensure the internal RPE logic starts up in
a known state. If this pin is tied to V
CC
, the RPE function will be disabled and the multiplexer will
function as a normal multiplexer. See “Application” section for more details. The CAP pin should
never be left open.
Reference Voltage: These outputs bias to V
CC
- 1.2V. They are used for AC-coupling inputs
(IN,/IN). Connect VREF_AC directly to the VT pin. Bypass with 0.01µF low ESR capacitor to
VCC. See "Input Interface Applications" section. Maximum sink/source current is ±1.5mA.
GND,
Exposed Pad
CAP
4,5
VREF-AC0
VREF-AC1
M9999-060410
hbwhelp@micrel.com or (408) 955-1690
3
Micrel, Inc.
Precision Edge
®
SY89837U
DETAILED FUNCTIONAL DESCRIPTION
RPE MUX and Fail-Safe Input
The SY89837U is optimized for clock switchover
applications where switching from one clock to another clock
without runt pulses (short cycles) is required. It features two
unique circuits:
1. Runt-Pulse Eliminator (RPE) Circuit
The RPE MUX provides a “glitchless” switchover between
two clocks and prevents any runt pulses from occurring
during the switchover transition. The design of both clock
inputs is identical (i.e., the switchover sequence and
protection is symmetrical for both input pair, IN0 or IN1. Thus,
either input pair may be defined as the primary input). If not
required, the RPE function can be permanently disabled to
allow the switchover between inputs to occur immediately.
For more detail on how to disable the RPE function within the
MUX, see the “Power-On Reset (POR)” section.
2. Fail-Safe Input (FSI) Circuit
RPE and FSI Functionality
The basic operation of the RPE MUX and FSI functionality
is described with the following four case descriptions. All
descriptions are related to the true inputs and outputs. The
primary (or selected) clock is called CLK1, the secondary
(or alternate) clock is called CLK2. Due to the totally
asynchronous relation of the IN and SEL signals and an
additional internal protection against metastability, the
number of pulses required for the operations described in
cases 1 through 4 can vary within certain limits. Refer to
“Timing Diagrams” and “Applications” section for detailed
information.
Case #1 Two Normal Clocks and RPE Enabled.
The FSI function provides protection against a selected
input pair that drops below the minimum amplitude
requirement. If the selected input pair drops sufficiently below
the 200mV minimum single-ended input amplitude limit (V
IN
),
or 400mV differentially (Vdiff_IN), the output will latch to the
last valid clock state.
In this case the frequency difference between the two
running clocks IN0 and IN1 must not be greater than 1.5:1.
For example, if the IN0 clock is 500MHz, the IN1 clock must
be within the range of 334MHz to 750MHz.
If the SEL input changes state to select the alternate
clock, the switchover from CLK1 to CLK2 will occur in three
stages:
•
Stage 1:
The output will continue to follow CLK1
for a limited number of pulses.
•
Stage 2:
The output will remain LOW for a lim-
ited number of pulses of CLK2.
•
Stage 3:
The output follows CLK2.
Figure 2. Timing Diagram 1
M9999-060410
hbwhelp@micrel.com or (408) 955-1690
4
Micrel, Inc.
Case #2 Input Clock Failure: Switching from a selected clock
stuck HIGH to a valid clock (RPE enabled).
Precision Edge
®
SY89837U
If CLK1 fails HIGH before the RPE MUX selects CLK2
(using the SEL pin), the switchover will occur in three
stages:
•
Stage 1:
The output will remain HIGH for a limited
number of pulses of CLK2.
•
Stage 2:
The output will switch to LOW and then
remain LOW for a limited number of falling edges
of CLK2.
•
Stage 3:
The output will follow CLK2.
Note:
Figure 3. Timing Diagram 2
(1)
1. Output shows extended clock cycle during switchover. Pulse width for both high and low of this cycle will always be greater than 50% of the CLK2
period.
Case #3 Input Clock Failure: Switching from a selected clock
stuck LOW to a valid clock (RPE enabled).
If CLK1 fails LOW before the RPE MUX selects CLK2
(using the SEL pin), the switchover will occur in two stages.
•
Stage 1:
The output will remain LOW for a lim-
ited number of falling edges of CLK2.
•
Stage 2:
The output will follow CLK2.
Figure 4. Timing Diagram 3
M9999-060410
hbwhelp@micrel.com or (408) 955-1690
5
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