Latch-up Current.................................................... > 200 mA
Operating Range
Range
Commercial
Industrial
Military
[4]
Ambient Temperature
0°C to +70°C
–40°C to +85–C
–55°C to +125°C
V
CC
5V ± 10%
5V ± 10%
5V ± 10%
Electrical Characteristics
Over the Operating Range
[5]
7C132-30
[3]
7C136-25,30
7C136-15
[3]
7C142-30
7C146-15 7C146-25,30
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
I
SB1
I
SB2
Description
Test Conditions
Output HIGH voltage V
CC
= Min., I
OH
= -4.0 mA
Output LOW voltage I
OL
= 4.0 mA
I
OL
= 16.0 mA
[6]
Input HIGH voltage
Input LOW voltage
Input load current
Output leakage
current
Output short circuit
current
[7]
V
CC
Operating
Supply Current
GND < V
I
< V
CC
GND < V
O
< V
CC
, Output Disabled
V
CC
= Max., V
OUT
= GND
CE = V
IL
, Outputs Open, f = Com’l
f
MAX[8]
Mil
Com’l
Mil
135
115
–5
–5
2.2
0.8
+5
+5
–350
190
75
−5
−5
2.4
0.4
0.5
2.2
0.8
+5
+5
−350
170
65
−5
−5
2.4
0.4
0.5
2.2
0.8
+5
+5
−350
120
170
45
65
90
115
15
15
15
15
125
105
85
105
−5
−5
7C132-35,45
7C136-35,45
7C142-35,45
7C146-35,45
2.4
0.4
0.5
2.2
0.8
+5
+5
7C132-55
7C136-55
7C142-55
7C146-55
2.4
0.4
0.5
V
V
µA
µA
V
V
Min. Max. Min. Max. Min. Max. Min. Max. Unit
−350
mA
110 mA
120
35
45
75
90
15
15
70
85
mA
mA
mA
mA
Standby current both CE
L
and CE
R
> V
IH
,
ports, TTL Inputs
f = f
MAX[8]
Standby Current
One Port,
TTL Inputs
Standby Current
Both Ports,
CMOS Inputs
Standby Current
One Port,
CMOS Inputs
CE
L
or CE
R
> V
IH
,
Com’l
Active Port Outputs Open, f Mil
= f
MAX[8]
Both Ports CE
L
and
CE
R
> V
CC
– 0.2V,
V
IN
> V
CC
– 0.2V or
V
IN
< 0.2V, f = 0
Com’l
Mil
I
SB3
I
SB4
One Port CEL or CER > V
CC
– Com’l
0.2V, V
IN
> V
CC
– 0.2V or V
IN
< Mil
0.2V, Active Port Outputs Open,
f = f
MAX[8]
Capacitance
[9]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
15
10
Unit
pF
pF
Shaded area contains preliminary information.
Notes:
4. T
A
is the “instant on” case temperature.
5. See the last page of this specification for Group A subgroup testing information.
6. BUSY and INT pins only.
7. Duration of the short circuit should not exceed 30 seconds.
8. At f=f
MAX
, address and data inputs are cycling at the maximum frequency of read cycle of 1/t
rc
and using AC Test Waveforms input levels of GND to 3V.
9. This parameter is guaranteed but not tested.
Document #: 38-06031 Rev. *B
Page 3 of 17
CY7C132/CY7C136
CY7C142/CY7C146
AC Test Loads and Waveforms
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
Equivalent to:
R2
347Ω
R1893Ω
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
R2
347Ω
BUSY
OR
INT
R1893Ω
5V
281Ω
30 pF
(a)
THÉVENIN EQUIVALENT
(b)
3.0V
BUSY Output Load
(CY7C132/CY7C136 Only)
ALL INPUT PULSES
10%
90%
90%
10%
< 5 ns
250Ω
OUTPUT
1.4V
GND
< 5 ns
Switching Characteristics
Over the Operating Range (Speeds -15, -25, -30)
[5, 10]
7C136-15
[3]
7C146-15
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
[14]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
R/W Pulse Width
Data Set-up to Write End
Data Hold from Write End
R/W LOW to High Z
[9]
R/W HIGH to Low Z
[9]
7C132-25
[3]
7C136-25
7C142-25
7C146-25
Min.
25
Max.
7C132-30
7C136-30
7C142-30
7C146-30
Min.
30
Max.
Unit
ns
30
0
30
20
3
15
5
15
0
25
30
25
25
2
0
25
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
0
ns
ns
Description
Read Cycle Time
Address to Data Valid
[11]
Data Hold from Address Change
CE LOW to Data Valid
[11]
OE LOW to Data Valid
[11]
OE LOW to Low Z
[9, 12]
OE HIGH to High
CE LOW to Low
Z
[9, 12, 13]
Z
[9, 12]
Min.
15
Max.
15
0
15
10
3
10
3
10
0
15
15
12
12
2
0
12
10
0
10
0
0
25
20
20
2
0
15
15
0
0
5
3
0
25
25
15
15
15
25
CE HIGH to High Z
[9, 12, 13]
CE LOW to Power-Up
[9]
CE HIGH to Power-Down
[9]
15
Shaded areas contain preliminary information.
Notes:
10. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified
I
OL
/I
OH,
and 30-pF load capacitance.
11. AC test conditions use V
OH
= 1.6V and V
OL
= 1.4V.
12. At any given temperature and voltage condition for any given device, t
HZCE
is less than t
LZCE
and t
HZOE
is less than t
LZOE
.
13. t
LZCE
, t
LZWE
, t
HZOE
, t
LZOE,
t
HZCE,
and t
HZWE
are tested with C
L
= 5pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
14. The internal write time of the memory is defined by the overlap of CE LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-06031 Rev. *B
Page 4 of 17
CY7C132/CY7C136
CY7C142/CY7C146
Switching Characteristics
Over the Operating Range (Speeds -15, -25, -30) (continued)
[5, 10]
7C136-15
[3]
7C146-15
Parameter
Busy/Interrupt Timing
t
BLA
t
BHA
t
BLC
t
BHC
t
PS
t
WB
t
WH
t
BDD
t
DDD
t
WDD
t
WINS
t
EINS
t
INS
t
OINR
t
EINR
t
INR
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
[15]
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH
[15]
Port Set Up for Priority
R/W LOW after BUSY LOW
[16]
R/W HIGH after BUSY HIGH
BUSY HIGH to Valid Data
Write Data Valid to Read Data Valid
Write Pulse to Data Delay
R/W to INTERRUPT Set Time
CE to INTERRUPT Set Time
Address to INTERRUPT Set Time
OE to INTERRUPT Reset Time
[15]
CE to INTERRUPT Reset Time
[15]
Address to INTERRUPT Reset Time
[15]
5
0
13
15
Note 17
Note 17
15
15
15
15
15
15
15
15
15
15
5
0
20
25
Note 17
Note 17
25
25
25
25
25
25
20
20
20
20
5
0
30
30
Note 17
Note 17
25
25
25
25
25
25
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
7C132-25
[3]
7C136-25
7C142-25
7C146-25
Min.
Max.
7C132-30
7C136-30
7C142-30
7C146-30
Min.
Max.
Unit
Interrupt Timing
[18]
Switching Characteristics
Over the Operating Range (Speeds -35, -45, -55)
[5, 10]
7C132-35
7C136-35
7C142-35
7C146-35
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Read Cycle Time
Address to Data Valid
[11]
Data Hold from Address Change
CE LOW to Data Valid
[11]
OE LOW to Data Valid
[11]
OE LOW to Low Z
[9, 12]
OE HIGH to High
CE LOW to Low
CE HIGH to High
Z
[9, 12, 13]
5
20
0
35
0
35
Z
[9, 12, 13]
Z
[9, 12]
3
20
5
20
0
35
0
35
20
3
20
5
25
35
35
0
45
25
3
25
45
45
0
55
25
55
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
7C132-45
7C136-45
7C142-45
7C146-45
Min.
Max.
7C132-55
7C136-55
7C142-55
7C146-55
Min.
Max.
Unit
CE LOW to Power-Up
[9]
CE HIGH to Power-Down
[9]
Notes:
15. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state.
16. CY7C142/CY7C146 only.
17. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:
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