Revision 3
Military ProASIC3/EL Low Power Flash FPGAs
with Flash*Freeze Technology
Features and Benefits
Military Temperature Tested and Qualified
• Each Device Tested from –55°C to 125°C
• Architecture Supports Ultra-High Utilization
Advanced and Pro (Professional) I/Os
††
•
•
•
•
•
•
•
•
•
•
•
•
•
•
700 Mbps DDR, LVDS-Capable I/Os
1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
†
Bank-Selectable I/O Voltages—up to 8 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X, and
LVCMOS 2.5 V / 5.0 V Input
†
Differential I/O Standards: LVPECL, LVDS, BLVDS, and M-LVDS
Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL
2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3
Class I and II (A3PE3000L only)
I/O Registers on Input, Output, and Enable Paths
Hot-Swappable and Cold-Sparing I/Os
Programmable Output Slew Rate and Drive Strength
Programmable Input Delay (A3PE3000L only)
Schmitt Trigger Option on Single-Ended Inputs (A3PE3000L)
Weak Pull-Up/-Down
IEEE 1149.1 (JTAG) Boundary Scan Test
Pin-Compatible Packages across the Military ProASIC
®
3EL Family
Firm-Error Immune
• Not Susceptible to Neutron-Induced Configuration Loss
Low Power
• Dramatic Reduction in Dynamic and Static Power
• 1.2 V to 1.5 V Core and I/O Voltage Support for Low Power
†
• Low Power Consumption in Flash*Freeze Mode Allows for
Instantaneous Entry To / Exit From Low-Power Flash*Freeze
Mode
ƒ
• Supports Single-Voltage System Operation
• Low-Impedance Switches
High Capacity
• 250K to 3M System Gates
• Up to 504 kbits of True Dual-Port SRAM
• Up to 620 User I/Os
Reprogrammable Flash Technology
•
•
•
•
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
Live-at-Power-Up (LAPU) Level 0 Support
Single-Chip Solution
Retains Programmed Design when Powered Off
Clock Conditioning Circuit (CCC) and PLL
• Six CCC Blocks—One Block with Integrated PLL in ProASIC3
and All Blocks with Integrated PLL in ProASIC3EL
• Configurable Phase Shift, Multiply/Divide, Delay Capabilities,
and External Feedback
• Wide Input Frequency Range 1.5 MHz to 250 MHz (1.2 V
systems) and 350 MHz (1.5 V systems)
High Performance
• 350 MHz (1.5 V systems) and 250 MHz (1.2 V systems) System
Performance
• 3.3 V, 66 MHz, 64-Bit PCI (1.5 V systems) and 66 MHz, 32-Bit
PCI (1.2 V systems)
SRAMs and FIFOs
• Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,
and ×18 organizations available)
• True Dual-Port SRAM (except ×18)
• 24 SRAM and FIFO Configurations with Synchronous
Operation:
– 250 MHz: For 1.2 V Systems
– 350 MHz: For 1.5 V Systems
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption via JTAG (IEEE 1532–compliant)
• FlashLock
®
to Secure FPGA Contents
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
• High-Performance, Low-Skew Global Network
Table 1 •
Military ProASIC3/EL Low-Power Devices
A3P250
ARM
®
Processor Support in ProASIC3/EL FPGAs
• ARM Cortex™-M1 Soft Processor Available with or without
Debug
A3PE600L
A3P1000
M1A3P1000
1M
24,576
144
32
1
Yes
1
18
4
154
A3PE3000L
M1A3PE3000L
3M
75,264
504
112
1
Yes
6
18
8
620
ProASIC3/EL Devices
Devices
1
ARM Cortex-M1
System Gates
250,000
600,000
VersaTiles (D-flip-flops)
6,144
13,824
RAM kbits (1,024 bits)
36
108
4,608-Bit Blocks
8
24
FlashROM Kbits
1
1
2
Secure (AES) ISP
Yes
Yes
Integrated PLL in CCCs
1
6
VersaNet Globals
18
18
I/O Banks
4
8
Maximum User I/Os
68
270
Package Pins
VQFP
VQ100
PQFP
FBGA
FG484
Notes:
1. Refer to the
Cortex-M1
product brief for more information.
2. AES is not available for ARM-enabled ProASIC3/EL devices.
† A3P250 and A3P1000 support only 1.5 V core operation.
ƒ Flash*Freeze technology is not available for A3P250 or A3P1000.
††Pro I/Os are not available on A3P250 or A3P1000.
September 2012
© 2011 Microsemi Corporation
PQ208
FG144, FG484
FG484, FG896
I
Military ProASIC3/EL Low Power Flash FPGAs
I/Os Per Package
1
ProASIC3/EL
Low Power Devices
ARM
Cortex-M1 Devices
Package
VQ100
PQ208
FG144
FG484
FG896
Differential
Single-
Single-
2
I/O Pairs Ended I/O
2
Ended I/O
68
–
–
–
–
13
–
–
–
–
–
–
–
270
–
Differential
I/O Pairs
–
–
–
135
–
A3P250
A3PE600L
A3P1000
M1A3P1000
A3PE3000L
M1A3PE3000L
Single-
Differential
Single- Differential
2
Ended I/O
I/O Pairs Ended I/O
2
I/O Pairs
–
154
97
300
–
–
35
25
74
–
–
–
–
341
620
–
–
–
168
300
Notes:
1. When considering migrating your design to a lower- or higher-density device, refer to the packaging section of the datasheet to
ensure you are complying with design and board migration requirements.
2. Each used differential I/O pair reduces the number of single-ended I/Os available by two.
3. "G" indicates RoHS-compliant packages. Refer to
"Military ProASIC3/EL Ordering Information" on page III
for the location of the
"G" in the part number.
4. For A3PE3000L devices, the usage of certain I/O standards is limited as follows:
– SSTL3(I) and (II): up to 40 I/Os per north or south bank
– LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank
– SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank
5. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not as a regular I/O, the number of single-ended
user I/Os available is reduced by one.
Military ProASIC3/EL Device Status
Military ProASIC3/EL Devices
A3P250
A3PE600L
A3P1000
A3PE3000L
Status
Production
Production
Production
Production
M1A3P1000
M1A3PE3000L
Production
Production
M1 Military ProASIC3/EL Devices
Status
II
R ev i si o n 3
Military ProASIC3/EL Low Power Flash FPGAs
Military ProASIC3/EL Ordering Information
A3P1000
_
1
FG
G
144
Y
M
Application (Temperature Range)
M = Military (
–
55°C to 125°C Junction Temperature)
Security Feature
Y = Device Includes License to Implement IP Based on the
Cryptography Research, Inc. (CRI) Patent Portfolio
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
G = RoHS-Compliant (Green) Packaging
Package Type
VQ = Very Thin Quad Flat Pack (0.5 mm pitch)
FG = Fine Pitch Ball Grid Array (1.0 mm pitch)
PQ = Plastic Quad Flat Pack (0.5 mm pitch)
Speed Grade
Blank = Standard
1 = 15% Faster than Standard
Part Number
Military ProASIC3/EL Devices
A3P250 = 250,000 System Gates
A3PE600L = 600,000 System Gates
A3P1000 = 1,000,000 System Gates
A3PE3000L = 3,000,000 System Gates
Military ProASIC3/EL Devices with ARM Cortex-M1
M1A3P1000 = 1,000,000 System Gates
M1A3PE3000L = 3,000,000 System Gates
R e visi on 3
III
Military ProASIC3/EL Low Power Flash FPGAs
Temperature Grade Offerings
Package
ARM Cortex-M1 Devices
VQ100
PQ208
FG144
FG484
FG896
M
–
–
–
–
–
–
–
M
–
A3P250
A3PE600L
A3P1000
M1A3P1000
–
M
M
M
–
A3PE3000L
M1A3PE3000L
–
–
–
M
M
Note:
M = Military temperature range: –55°C to 125°C junction temperature
Speed Grade and Temperature Grade Matrix
Temperature Grade
M
Std.
–1
✓
✓
Note:
M = Military temperature range: –55°C to 125°C junction temperature
Contact your local Microsemi SoC Products Group (formerly Actel) representative for device availability:
http://www.actel.com/contact/default.aspx.
IV
R ev i si o n 3
Military ProASIC3/EL Low Power Flash FPGAs
Table of Contents
Military ProASIC3/EL Device Family Overview
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Military ProASIC3/EL DC and Switching Characteristics
General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-112
Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-121
Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-125
Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-127
Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-148
JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-149
Pin Descriptions and Packaging
Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
User-Defined Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
User Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-1
3-2
3-2
3-4
3-5
3-5
3-5
Package Pin Assignments
VQ100
PQ208
FG144
FG484
FG896
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Revision 3
V
FPGA/CPLD
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