Hermetically Sealed, Very High Speed,
Logic Gate Optocouplers
Data Sheet
HCPL-540X,* 5962-89570, HCPL-543X, HCPL-643X, 5962-89571
*See matrix for available extensions.
Description
These units are single and dual channel, hermetically
sealed optocouplers. The products are capable of
operation and storage over the full military temperature
range and can be purchased as either standard product
or with full MIL-PRF-38534 Class Level H or K testing or
from the appropriate DSCC Drawing. All devices are
manufactured and tested on a MIL-PRF-38534 certified
line and are included in the DSCC Qualified Manufac-
turers List, QML-38534 for Hybrid Microcircuits.
Features
• Dual marked with device part number and DSCC
standard microcircuit drawing
• Manufactured and tested on a MIL-PRF-38534
certified line
• QML-38534, Class H and K
• Three hermetically sealed package configurations
• Performance guaranteed over full military
temperature range: -55°C to +125°C
• High Speed: 40 M bit/s
• High common mode rejection 500 V/µs guaranteed
• 1500 Vdc withstand test voltage
• Active (totem pole) outputs
• Three stage output available
• High radiation immunity
• HCPL-2400/30 function compatibility
• Reliability data
• Compatible with TTL, STTL, LSTTL, and HCMOS logic
families
Truth Tables
(Positive Logic)
Multichannel Devices
Input
On (H)
Off (L)
Single Channel DIP
Input
On (H)
Off (L)
On (H)
Off (L)
Enable
L
L
H
H
Output
L
H
Z
Z
Output
L
H
Applications
•
•
•
•
•
•
•
•
•
•
•
•
Military and space
High reliability systems
Transportation, medical, and life critical systems
Isolation of high speed logic systems
Computer-peripheral interfaces
Switching power supplies
Isolated bus driver (networking applications)-
(5400/1/K only)
Pulse transformer replacement
Ground loop elimination
Harsh industrial environments
High speed disk drive I/O
Digital isolation for A/D, D/A conversion
Functional Diagram
Multiple channel devices available
V
CC
V
E
V
O
GND
The connection of a 0.1
µ
F bypass capacitor between V
CC
and GND is recommended.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage
and/or degradation which may be induced by ESD.
Each channel contains an AlGaAs light emitting diode
which is optically coupled to an integrated high gain
photon detector. This combination results in very high
data rate capability. The detector has a threshold with
hysteresis, which typically provides 0.25 mA of differen-
tial mode noise immunity and minimizes the potential
for output signal chatter. The detector in the single
channel units has a three state output stage which
eliminates the need for a pull-up resistor and allows for
direct drive of a data bus.
All units are compatible with TTL, STTL, LSTTL, and
HCMOS logic families. The 35 ns pulse width distortion
specification guarantees a 10 MBd signaling rate at
+125°C with 35% pulse width distortion. Figures 13
through 16 show recommended circuits for reducing
pulse width distortion and optimizing the signal rate of
the product. Package styles for these parts are 8 pin
DIP through hole (case outlines P), and leadless ceramic
chip carrier (case outline 2). Devices may be purchased
with a variety of lead bend and plating options. See
Selection Guide Table for details. Standard Microcircuit
Drawing (SMD) parts are available for each package and
lead style.
Because the same electrical die (emitters and detectors)
are used for each channel of each device listed in this
data sheet, absolute maximum ratings, recommended
operating conditions, electrical specifications, and
performance characteristics shown in the figures are
similar for all parts. Occasional exceptions exist due to
package variations and limitations and are as noted.
Additionally, the same package assembly processes and
materials are used in all devices. These similarities give
justification for the use of data obtained from one part
to represent other part’s performance for die related
reliability and certain limited radiation test results.
Selection Guide–Package Styles and Lead Configuration Options
Package
Lead Style
Channels
Common Channel Wiring
Avago Part # & Options
Commercial
MIL-PRF-38534, Class H
MIL-PRF-38534, Class K
Standard Lead Finish
Solder Dipped*
Butt Cut/Gold Plate
Gull Wing/Soldered*
Class H SMD Part #
Prescript for all below
Either Gold or Solder
Gold Plate
Solder Dipped*
Butt Cut/Gold Plate
Butt Cut/Soldered*
Gull Wing/Soldered*
Class K SMD Part #
Prescript for all below
Either Gold of Solder
Gold Plate
Solder Dipped*
Butt Cut/Gold Plate
Butt Cut/Soldered*
Gull Wing/Soldered*
*Solder contains lead.
8 Pin DIP
Through Hole
1
None
HCPL-5400
HCPL-5401
HCPL-540K
Gold Plate
Option 200
Option 100
Option 300
5962-
8957001PX
8957001PC
8957001PA
8957001YC
8957001YA
8957001XA
5962-
8957002KPX
8957002KPC
8957002KPA
8957002KYC
8957002KYA
8957002KXA
8 Pin DIP
Through Hole
2
V
CC
, GND
HCPL-5430
HCPL-5431
HCPL-543K
Gold Plate
Option 200
Option 100
Option 300
5962-
8957101PX
8957101PC
8957101PA
8957101YC
8957101YA
8957101XA
5962-
8957103KPX
8957103KPC
8957103KPA
8957103KYC
8957103KYA
8957103KXA
20 Pad LCCC
Surface Mount
2
None
HCPL-6430
HCPL-6431
HCPL-643K
Solder Pads*
5962-
89571022X
89571022A
5962-
8957104K2X
8957104K2A
2
Functional Diagrams
8 Pin DIP
Through Hole
1 Channel
8 Pin DIP
Through Hole
2 Channels
V
CC
V
O1
20 Pad LCCC
Surface Mount
2 Channels
15
1
2
3
4
V
CC
V
E
8
7
6
5
1
2
3
4
8
V
CC2
19
V
O2
GND
2
V
O1
GND
1
V
CC1
13
12
7
V
O2
6
5
20
V
O
GND
2
3
10
GND
7
8
Note:
All DIP devices have common V
CC
and ground. LCCC (leadless ceramic chip carrier) package has isolated channels with separate V
CC
and
ground connections.
Outline Drawings
20 Terminal LCCC Surface Mount, 2 Channels
8.70 (0.342)
9.10 (0.358)
4.95 (0.195)
5.21 (0.205)
1.78 (0.070)
2.03 (0.080)
1.02 (0.040) (3 PLCS)
1.14 (0.045)
1.40 (0.055)
8.70 (0.342)
9.10 (0.358)
4.95 (0.195)
5.21 (0.205)
1.78 (0.070)
2.03 (0.080)
0.64
(0.025)
(20 PLCS)
1.52 (0.060)
2.03 (0.080)
TERMINAL 1 IDENTIFIER
2.16 (0.085)
METALLIZED
CASTILLATIONS (20 PLCS)
0.51 (0.020)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
SOLDER THICKNESS 0.127 (0.005) MAX.
;;;;
;;
;
9.40 (0.370)
9.91 (0.390)
0.76 (0.030)
1.27 (0.050)
0.51 (0.020)
MIN.
2.29 (0.090)
2.79 (0.110)
8 Pin DIP Through Hole, 1 and 2 Channel
8.13 (0.320)
MAX.
7.16 (0.282)
7.57 (0.298)
4.32 (0.170)
MAX.
3.81 (0.150)
MIN.
0.20 (0.008)
0.33 (0.013)
0.51 (0.020)
MAX.
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
7.36 (0.290)
7.87 (0.310)
3
Leaded Device Marking
Avago DESIGNATOR
Avago P/N
DSCC SMD*
DSCC SMD*
PIN ONE/
ESD IDENT
A QYYWWZ
XXXXXX
XXXXXXX
XXX XXX
•
50434
COMPLIANCE INDICATOR,*
DATE CODE, SUFFIX (IF NEEDED)
COUNTRY OF MFR.
Avago CAGE CODE*
Leadless Device Marking
Avago DESIGNATOR
Avago P/N
PIN ONE/
ESD IDENT
COUNTRY OF MFR.
A QYYWWZ
XXXXXX
•
XXXX
XXXXXX
XXX 50434
* QUALIFIED PARTS ONLY
COMPLIANCE INDICATOR,*
DATE CODE, SUFFIX (IF NEEDED)
DSCC SMD*
DSCC SMD*
Avago CAGE CODE*
* QUALIFIED PARTS ONLY
Hermetic Optocoupler Options
Option
100
Description
Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This
option is available on commercial and hi-rel product in 8 pin DIP (see drawings below for
details).
4.32 (0.170)
MAX.
0.51 (0.020)
MIN.
;;;
;
2.29 (0.090)
2.79 (0.110)
1.14 (0.045)
1.40 (0.055)
0.20 (0.008)
0.33 (0.013)
7.36 (0.290)
7.87 (0.310)
0.51 (0.020)
MAX.
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
200
300
Lead finish is solder dipped rather than gold plated. This option is available on commercial
and hi-rel product in 8 pin DIP. DSCC Drawing part numbers contain provisions for lead
finish. All leadless chip carrier devices are delivered with solder dipped terminals as a
standard feature.
Surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This
option is available on commercial and hi-rel product in 8 pin DIP (see drawings below for
details). This option has solder dipped leads.
0.51 (0.020)
MIN.
2.29 (0.090)
2.79 (0.110)
;;;
4.57 (0.180)
MAX.
0.20 (0.008)
0.33 (0.013)
9.65 (0.380)
9.91 (0.390)
4.57 (0.180)
MAX.
1.40 (0.055)
1.65 (0.065)
5° MAX.
0.51 (0.020)
MAX.
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
*Solder contains lead.
4
Absolute Maximum Ratings
No derating required up to +125°C.
Parameter
Storage Temperature
Operating Temperature
Case Temperature
Junction Temperature
Lead Solder Temperature
Average Forward Current (each channel)
Peak Input Current (each channel)
Reverse Input Voltage (each channel)
Supply Voltage
Average Output Current (each channel)
Output Voltage (each channel)
Output Power Dissipation (each channel)
Package Power Dissipation (each channel)
Single Channel Product Only
Three State Enable Voltage
Symbol
T
S
T
A
T
C
T
J
I
F(AVG)
I
F(PEAK)
V
R
V
CC
I
O(AVG)
V
O
P
O
P
D
Min.
-65
-55
Max.
+150
+125
+170
+175
260 for 10 sec
10
20
3
7.0
25
10
130
200
Units
°C
°C
°C
°C
°C
mA
mA
V
V
mA
V
mW
mW
Note
1
0.0
-25
-0.5
V
E
-0.5
10
V
8 Pin Ceramic DIP Single Channel Schematic
ANODE
2
+
V
F
3
–
CATHODE
I
E
I
CC
8
I
F
7
V
E
6
V
O
V
CC
5
GND
Note enable pin 7. An external 0.01
µF
to 0.1
µF
bypass capacitor must be connected
between V
CC
and ground for each package type.
ESD Classification
(MIL-STD-883, Method 3015)
HCPL-5400/01/0K
HCPL-5430/31/3K and HCPL-6430/31/3K
(▲▲), Class 2
(Dot), Class 3
Recommended Operating Conditions
Parameter
Input Current (High)
Supply Voltage, Output
Input Voltage (Low)
Fan Out (Each Channel)
Symbol
I
F(ON)
V
CC
V
F(OFF)
N
Min.
6
4.75
–
–
Max.
10
5.25
0.7
5
Units
mA
V
V
TTL Loads
Single Channel Product Only
High Level Enable Voltage
V
EH
Low Level Enable Voltage
V
EL
5
2.0
0
V
CC
0.8
V
V
嵌入式系统
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