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CY62138FV30LL-45ZAXIT

产品描述Standard SRAM, 256KX8, 45ns, CMOS, PDSO32, 8 X 13.40 MM, 1.20 MM HEIGHT, LEAD FREE, STSOP-32
产品类别存储    存储   
文件大小621KB,共20页
制造商Cypress(赛普拉斯)
标准  
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CY62138FV30LL-45ZAXIT概述

Standard SRAM, 256KX8, 45ns, CMOS, PDSO32, 8 X 13.40 MM, 1.20 MM HEIGHT, LEAD FREE, STSOP-32

CY62138FV30LL-45ZAXIT规格参数

参数名称属性值
是否无铅不含铅
是否Rohs认证符合
厂商名称Cypress(赛普拉斯)
包装说明TSSOP, TSSOP32,.56,20
Reach Compliance Codecompliant
ECCN代码3A991.B.2.A
最长访问时间45 ns
I/O 类型COMMON
JESD-30 代码R-PDSO-G32
JESD-609代码e4
长度11.8 mm
内存密度2097152 bit
内存集成电路类型STANDARD SRAM
内存宽度8
湿度敏感等级3
功能数量1
端子数量32
字数262144 words
字数代码256000
工作模式ASYNCHRONOUS
最高工作温度85 °C
最低工作温度-40 °C
组织256KX8
输出特性3-STATE
封装主体材料PLASTIC/EPOXY
封装代码TSSOP
封装等效代码TSSOP32,.56,20
封装形状RECTANGULAR
封装形式SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
并行/串行PARALLEL
峰值回流温度(摄氏度)260
电源2.5/3.3 V
认证状态Not Qualified
座面最大高度1.2 mm
最大待机电流0.000004 A
最小待机电流1.5 V
最大压摆率0.018 mA
最大供电电压 (Vsup)3.6 V
最小供电电压 (Vsup)2.2 V
标称供电电压 (Vsup)3 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子面层Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式GULL WING
端子节距0.5 mm
端子位置DUAL
处于峰值回流温度下的最长时间NOT SPECIFIED
宽度8 mm

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CY62138FV30 MoBL
®
2-Mbit (256 K × 8) Static RAM
2-Mbit (256 K × 8) Static RAM
Features
Functional Description
The CY62138FV30 is a high performance CMOS static RAM
organized as 256K words by 8 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL
) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption. Place the device into standby mode reducing
power consumption when deselected (CE
1
HIGH or CE
2
LOW).
To write to the device, take Chip Enable (CE
1
LOW and CE
2
HIGH) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O
0
through I/O
7
) is then written into the location specified
on the address pins (A
0
through A
17
).
To read from the device, take Chip Enable (CE
1
LOW and CE
2
HIGH) and Output Enable (OE) LOW while forcing Write Enable
(WE) HIGH. Under these conditions, the contents of the memory
location specified by the address pins appear on the I/O pins.
The eight input and output pins (I/O
0
through I/O
7
) are placed in
a high impedance state when the device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE
1
LOW and CE
2
HIGH and WE
LOW).
Very high-speed: 45 ns
Temperature ranges
Industrial: –40 °C to 85 °C
Automotive-A: –40 °C to 85 °C
Wide voltage range: 2.20 V to 3.60 V
Pin compatible with CY62138CV25/30/33
Ultra low standby power
Typical standby current: 1
A
Maximum standby current: 5
A
Ultra low active power
Typical active current: 1.6 mA at f = 1 MHz
Easy memory expansion with CE
1
, CE
2
, and OE Features
Automatic power down when deselected
Complementary metal oxide semiconductor (CMOS) for
Optimum speed and power
Offered in Pb-free 36-ball VFBGA, 32-pin TSOP II, 32-pin
SOIC, 32-pin TSOP I and 32-pin STSOP packages
Logic Block Diagram
Cypress Semiconductor Corporation
Document Number: 001-08029 Rev. *N
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised May 12, 2014

 
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