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CY14B101K
1 Mbit (128K x 8) nvSRAM With Real Time Clock
Features
■
■
■
❐
❐
■
■
■
25 ns
[1]
, 35 ns, and 45 ns access times
Pin compatible with STK17TA8
Data integrity of Cypress nvSRAM combined with full featured
Real Time Clock (RTC)
❐
Low power, 350 nA RTC current
❐
Capacitor or battery backup for RTC
Watchdog timer
Clock alarm with programmable interrupts
Hands off automatic STORE on power down with only a small
capacitor
STORE to QuantumTrap™ initiated by software, device pin, or
on power down
RECALL to SRAM initiated by software or on power up
Infinite READ, WRITE, and RECALL cycles
High reliability
Endurance to 200K cycles
Data retention: 20 years at 55°C
Single 3V operation with tolerance of +20%, –10%
Commercial and industrial temperature
48-Pin SSOP package (ROHS compliant)
Functional Description
■
■
■
■
■
■
■
Logic Block Diagram
A
5
A
6
A
7
A
8
A
9
A
12
A
13
A
14
A
15
A
16
de
d
fo
r
en
QuantumTrap
1024 x 1024
STORE
RECALL
The Real Time Clock function provides an accurate clock with
leap year tracking and a programmable high accuracy oscillator.
The alarm function is programmable for one time alarm or
periodic seconds, minutes, hours, or days. There is also a
programmable watchdog timer for process control.
N
V
CC
ROW DECODER
m
om
STATIC RAM
ARRAY
1024 X 1024
ew
V
CAP
POWER
CONTROL
STORE/
RECALL
CONTROL
RTC
MUX
The Cypress CY14B101K combines a 1 Mbit nonvolatile static
RAM with a full featured real time clock in a monolithic integrated
circuit. The embedded nonvolatile elements incorporate
QuantumTrap technology producing the world’s most reliable
nonvolatile memory. The SRAM is read and written an infinite
number of times, while independent, nonvolatile data resides in
the nonvolatile elements.
SOFTWARE
DETECT
COLUMN IO
COLUMN DEC
D
V
RTCbat
V
RTCcap
R
DQ
2
DQ
4
INPUT BUFFERS
ec
DQ
0
DQ
1
DQ
3
ot
DQ
5
DQ
6
A
0
A
1
A
2
A
3
A
4
A
10
A
11
DQ
7
N
Note
1. 25 ns speed in Industrial temperature range is over the operating voltage range of 3.3V+ 0.3V only.
Cypress Semiconductor Corporation
Document Number: 001-06401 Rev. *L
•
198 Champion Court
•
San Jose
,
CA 95134-1709
es
HSB
ig
ns
A
15
-
A
0
x
1
x
2
INT
A
16
-
A
0
OE
CE
WE
•
408-943-2600
Revised April 5, 2010
[+] Feedback
CY14B101K
Contents
Features .............................................................................. 1
Functional Description ....................................................... 1
Logic Block Diagram .......................................................... 1
Contents .............................................................................. 2
Pin Configurations ............................................................. 3
Device Operation ................................................................ 4
SRAM READ ................................................................. 4
SRAM WRITE ............................................................... 4
AutoStore® Operation ................................................... 4
Hardware STORE (HSB) Operation .............................. 4
Hardware RECALL (Power Up) ..................................... 5
Software STORE ........................................................... 5
Software RECALL ......................................................... 5
Data Protection ............................................................. 5
Noise Considerations .................................................... 5
Low Average Active Power ........................................... 6
Best Practices ............................................................... 6
Real Time Clock Operation ................................................ 8
nvTIME Operation ......................................................... 8
Clock Operations ........................................................... 8
Reading the Clock ......................................................... 8
Setting the Clock ........................................................... 8
Backup Power ............................................................... 8
Stopping and Starting the Oscillator .............................. 8
Calibrating the Clock ..................................................... 9
Alarm ............................................................................. 9
Watchdog Timer ............................................................ 9
Power Monitor ............................................................. 10
Interrupts ..................................................................... 10
Interrupt Register ........................................................ 10
Flags Register ............................................................. 10
Maximum Ratings ............................................................. 16
Operating Range .............................................................. 16
DC Electrical Characteristics .......................................... 16
Data Retention and Endurance ....................................... 17
Capacitance ...................................................................... 17
Thermal Resistance ......................................................... 17
AC Test Conditions .......................................................... 17
AC Switching Characteristics ......................................... 18
AC Switching Characteristics (continued) ..................... 19
AutoStore or Power Up RECALL .................................... 20
Software Controlled STORE/RECALL Cycles
................ 21
Hardware STORE Cycle ................................................... 22
Soft Sequence Commands .............................................. 22
RTC Characteristics ......................................................... 23
Truth Table For SRAM Operations ................................. 23
Part Numbering Nomenclature ....................................... 24
Ordering Information ....................................................... 25
Package Diagrams ........................................................... 26
Document History Page ................................................... 27
Sales, Solutions, and Legal Information ........................ 29
Worldwide Sales and Design Support ......................... 29
Products ...................................................................... 29
Document Number: 001-06401 Rev. *L
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CY14B101K
Pin Configurations
Figure 1. 48-Pin SSOP
V
CAP
A
16
A
14
A
12
A
7
A
6
A
5
INT
A
4
NC
NC
NC
V
SS
NC
V
RTCbat
DQ0
A
3
A
2
A
1
A
0
DQ1
DQ2
x
1
x
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
V
CC
A
15
HSB
WE
A
13
A
8
A
9
NC
NC
39
38
37
ew
34
33
(Not To Scale)
N
fo
r
d
en
de
Table 1. Pin Definitions
Pin Name
A
0
– A
16
DQ0 – DQ7
NC
WE
CE
OE
X
1
X
2
V
RTCcap
V
RTCbat
INT
V
SS
V
CC
HSB
W
E
G
Alt
I/O Type
Input
Input Output
No Connect
Input
Input
Input
Description
Bidirectional Data I/O Lines.
Used as input or output lines depending on operation
No Connects.
This pin is not connected to the die
Write Enable Input, Active LOW.
When the chip is enabled and WE is LOW, data on the I/O pins
is written to the specific address location.
Chip Enable Input, Active LOW.
When LOW, selects the chip. When HIGH, deselects the chip.
Output Enable, Active LOW.
The active low OE input enables the data output buffers during
READ cycles. Deasserting OE high causes the I/O pins to tri-state.
Crystal Connection
Drives crystal on start up.
Crystal Connection
for 32.768 kHz crystal.
N
ot
R
Power Supply
Capacitor Supplied Backup RTC Supply Voltage.
(Left unconnected if V
RTCbat
is used)
Power Supply
Battery Supplied Backup RTC Supply Voltage.
(Left unconnected if V
RTCcap
is used)
Output
Ground
Input Output
Interrupt Output.
Program to respond to the clock alarm, the watchdog timer, and the power
monitor. Programmable to either active HIGH (push or pull) or LOW (open drain).
Ground for the Device.
Must be connected to ground of the system.
Hardware Store Busy.
When LOW this output indicates a Hardware Store is in progress. When
pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull up
resistor keeps this pin HIGH if not connected (connection optional).
Power Supply
Power Supply Inputs to the Device.
V
CAP
Power Supply
AutoStore™ Capacitor.
Supplies power to nvSRAM during power loss to store data from SRAM
to nonvolatile elements.
Page 3 of 29
Document Number: 001-06401 Rev. *L
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Output
Input
om
m
Address Inputs.
Used to select one of the 131,072 bytes of the nvSRAM.
D
36
35
32
31
30
29
28
27
26
25
Top View
es
NC
NC
V
SS
NC
V
RTCcap
DQ
6
OE
A
10
CE
DQ7
DQ5
DQ4
DQ3
V
CC
48-SSOP
40
A
11
ig
ns
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CY14B101K
Device Operation
The CY14B101K nvSRAM consists of two functional compo-
nents paired in the same physical cell. The components are
SRAM memory cell and a nonvolatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM. Data
in the SRAM is transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to SRAM (the RECALL
operation). Using this unique architecture, all cells are stored and
recalled in parallel. During the STORE and RECALL operations,
SRAM READ and WRITE operations are inhibited. The
CY14B101K supports infinite reads and writes similar to a typical
SRAM. In addition, it provides infinite RECALL operations from
the nonvolatile cells and up to 200K STORE operations.
See the
“Truth Table For SRAM Operations”
on page 23 for a
complete description of read and write modes.
automatically disconnects the V
CAP
pin from V
CC
. A STORE
operation is initiated with power provided by the V
CAP
capacitor.
Figure 2. AutoStore Mode
V
CC
V
CAP
V
CAP
V
CC
ig
ns
WE
10k Ohm
SRAM READ
The CY14B101K performs a READ cycle whenever CE and OE
are LOW while WE and HSB are HIGH. The address specified
on pins A
0-16
determines which of the 131,072 data bytes are
accessed. When the READ is initiated by an address transition,
the outputs are valid after a delay of t
AA
(see
Figure 8
on page
18). If the READ is initiated by CE or OE, the outputs are valid at
t
ACE
or at t
DOE
, whichever is later (see
Figure 9
on page 18). The
data outputs repeatedly respond to address changes within the
t
AA
access time without the need for transitions on any control
input pins. This remains valid until another address change or
until CE or OE is brought HIGH, or WE or HSB is brought LOW.
AutoStore
®
Operation
AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the CY14B101K.
During normal operations, the device draws current from V
CC
to
charge a capacitor connected to the V
CAP
pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the V
CC
pin drops below V
SWITCH
, the part
Document Number: 001-06401 Rev. *L
N
The CY14B101K stores data to nvSRAM using one of three
storage operations:
1. Hardware Store activated by HSB
2. Software Store activated by an address sequence
3. AutoStore on device power down
R
ec
A WRITE cycle is performed whenever CE and WE are LOW and
HSB is HIGH. The address inputs must be stable before entering
the WRITE cycle and must remain stable until either CE or WE
go HIGH at the end of the cycle. The data on the common I/O
pins DQ
0–7
is written into the memory if the data is valid t
SD
before the end of a WE controlled WRITE or before the end of
an CE controlled WRITE. Keep OE HIGH during the entire
WRITE cycle to avoid data bus contention on common I/O lines.
If OE is left LOW, internal circuitry turns off the output buffers
t
HZWE
after WE goes LOW.
om
m
en
de
SRAM WRITE
ot
d
fo
r
Figure 2
shows the proper connection of the storage capacitor
(V
CAP
) for automatic store operation. Refer to
DC Electrical
Characteristics
on page 16 for the size of the V
CAP
. The voltage
on the V
CAP
pin is driven to 5V by a charge pump internal to the
chip. A pull up should be placed on WE to hold it inactive during
power up. This pull up is only effective if the WE signal is tri-state
during power up. Many MPUs tri-state their controls on power up.
Verify this when using the pull up. When the nvSRAM comes out
of power-on-recall, the MPU must be active or the WE held
inactive until the MPU comes out of reset.
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware Store operations are ignored unless at least one
WRITE operation takes place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a WRITE operation took place. Monitor the
HSB signal by the system to detect if an AutoStore cycle is in
progress.
Hardware STORE (HSB) Operation
The CY14B101K provides the HSB pin for controlling and
acknowledging the STORE operations. Use the HSB pin to
request a hardware STORE cycle. When the HSB pin is driven
LOW, the CY14B101K conditionally initiates a STORE operation
after t
DELAY
. An actual STORE cycle only begins if a WRITE to
the SRAM has taken place since the last STORE or RECALL
cycle. The HSB pin also acts as an open drain driver that is inter-
nally driven LOW to indicate a busy condition while the STORE
(initiated by any means) is in progress. This pin is externally
pulled up if it is used to drive other inputs.
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ew
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