PRELIMINARY
CY7C1305V25
CY7C1307V25
18-Mb Burst of 4 Pipelined SRAM with QDR™ Architecture
Features
• Separate independent Read and Write data ports
— Supports concurrent transactions
• 167-MHz clock for high bandwidth
— 2.5 ns Clock-to-Valid access time
• 4-Word Burst for reducing the address bus frequency
• Double Data Rate (DDR) interfaces on both Read & Write
Ports (data transferred at 333 MHz) @167 MHz
• Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
• Two output clocks (C and C) accounts for clock skew
and flight time mismatching
• Single multiplexed address input bus latches address
inputs for both Read and Write ports
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• 2.5V core power supply with HSTL Inputs and Outputs
• 13 x 15 x 1.2 mm 1.0-mm pitch fBGA package, 165 ball
(11x15 matrix)
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V–1.9V)
• JTAG Interface
Functional Description
The CY7C1305V25/CY7C1307V25 are 2.5V Synchronous
Pipelined SRAMs equipped with QDR architecture. QDR
architecture consists of two separate ports to access the
memory array. The Read port has dedicated Data Outputs to
support Read operations and the Write Port has dedicated
Data Inputs to support Write operations. QDR architecture has
separate data inputs and data outputs to completely eliminate
the need to “turn-around” the data bus required with common
I/O devices. Access to each port is accomplished through a
common address bus. Addresses for Read and Write
addresses are latched on alternate rising edges of the input
(K) clock. Accesses to the device’s Read and Write ports are
completely independent of one another. In order to maximize
data throughput, both Read and Write ports are equipped with
Double Data Rate (DDR) interfaces. Each address location is
associated with four 18-bit words (CY7C1305V25) and four
36-bit words (CY7C1307V25) that burst sequentially into or
out of the device. Since data can be transferred into and out
of the device on every rising edge of both input clocks (K/K and
C/C) memory bandwidth is maximized while simplifying
system design by eliminating bus “turn-arounds.”
Depth expansion is accomplished with Port Selects for each
port. Port selects allow each port to operate independently.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Configurations
CY7C1305V25 – 1 Mb x 18
CY7C1307V25 – 512K x 36
Logic Block Diagram (CY7C1305V25)
D
[17:0]
18
Write Write
Reg
Reg
Write Write
Reg
Reg
Write Add. Decode
18
Read Add. Decode
A
[17:0]
Address
Register
Address
Register
256Kx18 Array
256Kx18 Array
256Kx18 Array
256Kx18 Array
18
A
(17:0)
K
K
CLK
Gen.
Control
Logic
RPS
C
C
Read Data Reg.
Vref
WPS
BWS
[0:1]
72
Control
Logic
36
36
Reg.
Reg.
18
Reg.
18
Q
[17:0]
Cypress Semiconductor Corporation
Document #: 38-05099 Rev. *B
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised February 2, 2004
PRELIMINARY
CY7C1305V25
CY7C1307V25
Logic Block Diagram (CY7C1307V25)
D
[35:0]
36
Write Write
Reg
Reg
Write Write
Reg
Reg
Write Add. Decode
17
Read Add. Decode
A
(16:0)
Address
Register
Address
Register
128K x 36 Array
128K x 36 Array
128K x 36 Array
128K x 36 Array
17
A
(16:0)
K
K
CLK
Gen.
Control
Logic
RPS
C
C
Read Data Reg.
Vref
WPS
BWS
[0:3]
144
Control
Logic
72
72
Reg.
Reg.
36
Reg.
36
Q
[35:0]
Selection Guide
7C1305V25-167
7C1307V25-167
Maximum Operating Frequency
Maximum Operating Current
167
550
7C1305V25-133
7C1307V25-133
133
470
7C1305V25-100
7C1307V25-100
100
420
Unit
MHz
mA
Document #: 38-05099 Rev. *B
Page 2 of 23
PRELIMINARY
Pin Configuration - CY7C1305V25 (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
TDO
2
Gnd/
144M
Q9
NC
D11
NC
Q12
D13
VREF
NC
NC
Q15
NC
D17
NC
TCK
3
NC/ 36M
D9
D10
Q10
Q11
D12
Q13
VDDQ
D14
Q14
D15
D16
Q16
Q17
A
4
WPS
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
A
5
BWS
1
NC
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
A
A
6
K
K
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
C
C
7
NC
BWS
0
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
A
A
8
RPS
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
A
9
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
CY7C1305V25
CY7C1307V25
10
Gnd/
72M
NC
Q7
NC
D6
NC
NC
VREF
Q4
D3
NC
Q1
NC
D0
TMS
11
NC
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
Pin Configuration - CY7C1307V25 (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC
Q27
D27
D28
Q29
Q30
D30
NC
D31
Q32
Q33
D33
D34
Q35
TDO
2
Gnd/
288M
Q18
Q28
D20
D29
Q21
D22
VREF
Q31
D32
Q24
Q34
D26
D35
TCK
3
NC/ 72M
D18
D19
Q19
Q20
D21
Q22
VDDQ
D23
Q23
D24
D25
Q25
Q26
A
4
WPS
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
A
5
BWS
2
BWS
3
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
A
A
6
K
K
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
C
C
7
BWS
1
BWS
0
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
A
A
8
RPS
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
A
9
NC/
36M
D17
D16
Q16
Q15
D14
Q13
VDDQ
D12
Q12
D11
D10
Q10
Q9
A
10
Gnd/
144M
Q17
Q7
D15
D6
Q14
D13
VREF
Q4
D3
Q11
Q1
D9
D0
TMS
11
NC
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
Document #: 38-05099 Rev. *B
Page 3 of 23
PRELIMINARY
Pin Definitions
Name
D
[x:0]
I/O
Input-
Synchronous
Description
CY7C1305V25
CY7C1307V25
Data input signals, sampled on the rising edge of K and K clocks during valid
write operations.
CY7C1305V25 – D
[17:0]
CY7C1307V25 – D
[35:0]
Write Port Select, active LOW.
Sampled on the rising edge of the K clock. When
asserted active, a Write operation is initiated. Deasserting will deselect the Write port.
Deselecting the Write port will cause D
[x:0]
to be ignored.
Byte Write Select 0, 1, 2, and 3 - active LOW.
Sampled on the rising edge of the K
and K clocks during Write operations. Used to select which byte is written into the device
during the current portion of the Write operations. Bytes not written remain unaltered.
CY7C1305V25 - BWS
0
controls D
[8:0]
and BWS
1
controls D
[17:9].
CY7C1307V25 - BWS
0
controls D
[8:0]
, BWS
1
controls D
[17:9]
, BWS
2
controls D
[26:18]
and BWS
3
controls D
[35:27]
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a
Byte Write Select will cause the corresponding byte of data to be ignored and not written
into the device.
Address Inputs.
Sampled on the rising edge of the K clock during active Read and
Write operations. These address inputs are multiplexed for both Read and Write oper-
ations. Internally, the device is organized as 1M x 18 (4 arrays each of 256K x 18) for
CY7C1305V25 and 512K x 36 (4 arrays each of 128K x 36) for CY7C1307V25. There-
fore, only 18 address inputs for CY7C1305V25 and 17 address inputs for
CY7C1307V25. These inputs are ignored when the appropriate port is deselected.
Data Output signals.
These pins drive out the requested data during a Read operation.
Valid data is driven out on the rising edge of both the C and C clocks during Read
operations or K and K when in single clock mode. When the Read port is deselected,
Q
[x:0]
are automatically three-stated.
CY7C1305V25 - Q
[17:0]
CY7C1307V25 - Q
[35:0]
Read Port Select, active LOW.
Sampled on the rising edge of Positive Input Clock (K).
When active, a Read operation is initiated. Deasserting will cause the Read port to be
deselected. When deselected, the pending access is allowed to complete and the out-
put drivers are automatically three-stated following the next rising edge of the C clock.
Each read access consists of a burst of four sequential 18-bit or 36-bit transfers.
Positive Output Clock Input.
C is used in conjunction with C to clock out the Read
data from the device. C and C can be used together to deskew the flight times of various
devices on the board back to the controller. See application example for further details.
Negative Output Clock Input.
C is used in conjunction with C to clock out the Read
data from the device. C and C can be used together to deskew the flight times of various
devices on the board cack to the controller. See application example for further details.
Positive Input Clock Input.
The rising edge of K is used to capture synchronous inputs
to the device and to drive out data through Q
[x:0]
when in single clock mode. All accesses
are initiated on the rising edge of K.
Negative Input Clock Input.
K is used to capture synchronous inputs to the device and
to drive out data through Q
[x:0]
when in single clock mode.
Output Impedance Matching Input.
This input is used to tune the device outputs to
the system data bus impedance. Q
[x:0]
output impedance are set to 0.2 x RQ, where
RQ is a resistor connected between ZQ and ground. Alternately, this pin can be con-
nected directly to V
DD
, which enables the minimum impedance mode. This pin cannot
be connected directly to GND or left unconnected.
TDO pin for JTAG
TCK pin for JTAG
TDI pin for JTAG
TMS pin for JTAG
Address expansion for 36M.
This is not connected to the die. Can be connected to
any voltage level on CY7C1305V25/CY7C1307V25.
Page 4 of 23
WPS
Input-
Synchronous
Input-
Synchronous
BWS
0
, BWS
1
,
BWS
2
, BWS
3
A
Input-
Synchronous
Q
[x:0]
Outputs-
Synchronous
RPS
Input-
Synchronous
C
Input-Clock
C
Input-Clock
K
Input-Clock
K
ZQ
Input-Clock
Input
TDO
TCK
TDI
TMS
NC/36M
Output
Input
Input
Input
N/A
Document #: 38-05099 Rev. *B
PRELIMINARY
Pin Definitions
(continued)
Name
GND/72M
NC/72M
GND/144M
GND/288M
V
REF
V
DD
V
SS
V
DDQ
NC
I/O
Input
N/A
Input
Input
Input-
Reference
Power Supply
Ground
Power Supply
N/A
Description
CY7C1305V25
CY7C1307V25
Address expansion for 72M.
This should be tied LOW on the CY7C1305V25.
Address expansion for 72M.
This can be connected to any voltage level on
CY7C1307V25.
Address expansion for 144M.
This should be tied LOW on
CY7C1305V25/CY7C1307V25.
Address expansion for 144M.
This should be tied LOW on CY7C1307V25.
Reference Voltage Input.
Static input used to set the reference level for HSTL inputs
and Outputs as well as AC measurement points.
Power supply inputs to the core of the device
Ground for the device
Power supply inputs for the outputs of the device
Not connected to the die.
Can be tied to any voltage level.
onto the Q
[17:0]
. This process continues until all four 18-bit data
words have been driven out onto Q
[17:0]
. The requested data
will be valid 2.5 ns from the rising edge of the output clock
(C and C, or K and K when in single clock mode, 167-MHz
device). In order to maintain the internal logic, each Read
access must be allowed to complete. Each Read access
consists of four 18-bit data words and takes 2 clock cycles to
complete. Therefore, Read accesses to the device can not be
initiated on two consecutive K clock rises. The internal logic of
the device will ignore the second Read request. Read
accesses can be initiated on every other K clock rise. Doing
so will pipeline the data flow such that data is transferred out
of the device on every rising edge of the output clocks (C and
C, or K and K when in single clock mode).
When the read port is deselected, the CY7C1305V25 will first
complete the pending read transactions. Synchronous internal
circuitry will automatically three-state the outputs following the
next rising edge of the positive output clock (C). This will allow
for a seamless transition between devices without the
insertion of wait states in a depth expanded memory.
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the positive input clock (K). On the following K
clock rise the data presented to D
[17:0]
is latched and stored
into the lower 18-bit Write Data register provided BWS
[1:0]
are
both asserted active. On the subsequent rising edge of the
negative input clock (K) the information presented to D
[17:0]
is
also stored into the Write Data Register provided BWS
[1:0]
are
both asserted active. This process continues for one more
cycle until four 18-bit words (a total of 72 bits) of data are
stored in the SRAM. The 72 bits of data are then written into
the memory array at the specified location. Therefore, Write
accesses to the device can not be initiated on two consecutive
K clock rises. The internal logic of the device will ignore the
second Write request. Write accesses can be initiated on
every other rising edge of the positive clock (K). Doing so will
pipeline the data flow such that 18-bits of data can be trans-
ferred into the device on every rising edge of the input clocks
(K and K).
When deselected, the write port will ignore all inputs after the
pending Write operations have been completed.
Introduction
Functional Overview
The
CY7C1305V25/CY7C1307V25
are
synchronous
pipelined Burst SRAMs equipped with both a Read port and a
Write port. The Read port is dedicated to Read operations and
the Write Port is dedicated to Write operations. Data flows into
the SRAM through the Write port and out through the Read
port. These devices multiplex the address inputs in order to
minimize the number of address pins required. By having
separate Read and Write ports, the device completely elimi-
nates the need to “turn-around” the data bus and avoids any
possible data contention, thereby simplifying system design.
Each access consists of four 18-bit data transfers in the case
of CY7C1305V25 and four 36-bit data transfers in the case of
CY7C1307V25, in two clock cycles.
Accesses for both ports are initiated on the rising edge of the
positive input clock (K). All synchronous input timing is refer-
enced from the rising edge of the input clocks (K and K) and
all output timing is referenced to the rising edge of output
clocks (C and C, or K and K when in single clock mode).
All synchronous data inputs (D
[x:0]
) pass through input
registers controlled by the rising edge of input clocks (K and
K). All synchronous data outputs (Q
[x:0]
) pass through output
registers controlled by the rising edge of the output clocks (C
and C, or K and K when in single clock mode).
All synchronous control (RPS, WPS, BWS
[0:x]
) inputs pass
through input registers controlled by the rising edge of input
clocks (K and K).
CY7C1305V25 is described in the following sections. The
same basic descriptions apply to CY7C1307V25.
Read Operations
The CY7C1305V25 is organized internally as 4 arrays of 256K
x 18. Accesses are completed in a burst of four sequential
18-bit data words. Read operations are initiated by asserting
RPS active at the rising edge of the Positive Input Clock (K).
The address presented to Address inputs are stored in the
Read address register. Following the next K clock rise the
corresponding lowest order 18-bit word of data is driven onto
the Q
[17:0]
using C as the output timing reference. On the
subsequent rising edge of C the next 18-bit data word is driven
Document #: 38-05099 Rev. *B
Page 5 of 23
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