Internet Data Sheet
IDGV1G-05A1F1C
1GBit GDDR5 Graphics RAM
IDGV1G-05A1F1C–[40X/50X/55X]
Revision History:2008-12, Rev. 1.10
Page
All
All
5
All
All
Subjects (major changes since last revision)
Speed bin -55X added, speed bin -45X removed
Typos corrected
Figure1 - Maximum data rate for RDQS mode increased to 3.0 Gbps; PLL-off mode restricted to 4.0 Gbps
36X speed bin removed
Adapted Internet version
Previous Revision: Rev. 1.01, 2008-10
Previous Revision: Rev. 1.00, 2008-09
Previous Revision: Rev. 0.60, 2008-06
Previous Revision: Rev. 0.50, 2008-05
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qag_techdoc_A4, 4.22, 2008-07-22
05272008-QT8C-2TYT
2
Internet Data Sheet
IDGV1G-05A1F1C
1GBit GDDR5 Graphics RAM
1
1.1
Overview
Features
• Read/Write data transmission integrity secured by cyclic
redundancy check (CRC–8)
• Auto Precharge option for each burst access
• Programmable CAS latency: 6 to 20
t
CK
• Programmable Write latency: 3 to 7
t
CK
• Programmable CRC READ latency: 0 to 2
t
CK
• Programmable CRC WRITE latency: 8 to 11
t
CK
• Digital
t
RAS
lockout
• RDQS mode on EDC pin
• Data output mode for Vendor ID, density and FIFO depth
• Low Power modes
• On-chip temperature sensor with read-out
• Auto refresh and self refresh modes
• 32ms data retention (8k cycles)
• Automatic temperature sensor controlled self refresh rate
• On-die termination (ODT): nom. values of 60
Ω
or 120
Ω
• Pseudo open drain (POD–15) compatible outputs (40
Ω
pulldown, 60
Ω
pullup)
• ODT and output driver strength auto-calibration with
external resistor ZQ pin (120
Ω)
• Programmable termination and driver strength offsets
• Selectable external or internal VREF for data inputs;
programmable offsets for internal VREF
• Separate external VREF for address / command inputs
• Boundary Scan function with SEN pin
• Mirror function with MF pin
•
V
DD
1.5V +/- 3%
•
V
DDQ
1.5V +/- 3%
• PG-TFBGA 170
• RoHS Compliant Product
1)
• Monolithic 1Gbit GDDR5 SGRAM (2Mbit x 32 I/O x 16
banks and 4Mbit x 16 I/O x 16 banks)
• x32/x16 mode configuration set at power-up with EDC pin
• Quarter data-rate differential clock inputs CK/CK for
address and commands
• Two half data-rate differential clock inputs WCK/WCK,
each associated with two data bytes (DQ, DBI, EDC)
• Single ended interface for data, address and command
• Double Data Rate (DDR) data (WCK)
• Single Data Rate (SDR) command (CK)
• Double Data Rate (DDR) addressing (CK)
• Write data mask function (single/double byte mask) via
address bus
• 16 internal banks
• 4 bank groups for
t
CCD
= 3
t
CK
• 8n prefetch architecture: 256 bit per array Read or Write
access
• Burst Length: 8 only
• Data bus inversion (DBI) and address bus inversion (ABI)
• Input/output PLL on/off mode
• Address training: address input monitoring via DQ pins
• WCK2CK clock training: phase information via EDC pins
• Data read and write training via Read FIFO
(FIFO depth = 6)
• Read FIFO pattern preload by LDFF command
• Direct write data load to Read FIFO by WRTR command
• Consecutive read of Read FIFO by RDTR command
• Programmable EDC hold pattern for CDR
• Data Preamble for Read
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.10, 2008-12
05272008-QT8C-2TYT
3
Internet Data Sheet
IDGV1G-05A1F1C
1GBit GDDR5 Graphics RAM
TABLE 1
Ordering Information
Part Number
1)
IDGV1G-05A1F1C – 40X
IDGV1G-05A1F1C – 50X
IDGV1G-05A1F1C – 55X
Organization
×32
/ x16
Max. Data Rate
(Gbps/pin)
4.0
5.0
5.5
Package
PG-TFBGA 170
1) I: Qimonda Identifier, D: DRAM, GV: GDDR5, 1G: 1Gbit, 0: 1 x CS, 5: x32, A1: 1st node, F1: FBGA, C: Commercial 0° - 85/95°C
1.2
Description
The Qimonda GDDR5 SGRAM is a high speed dynamic random-access memory designed for applications requiring high
bandwidth. It contains 1,073,741,824 bits and is internally configured as a 16-bank DRAM.
The GDDR5 SGRAM uses a 8n prefetch architecture and DDR interface to achieve high-speed operation. It can be configured
to operate in x32 mode or x16 (clamshell) mode. The mode is detected during device initialization. The GDDR5 interface
transfers two 32 bit wide data words per WCK clock cycle to/from the I/O pins. Corresponding to the 8n prefetch a single write
or read access consists of a 256 bit wide, two CK clock cycle data transfer at the internal memory core and eight corresponding
32 bit wide one-half WCK clock cycle data transfers at the I/O pins.
The GDDR5 SGRAM operates from a differential clock CK and CK. Commands are registered at every rising edge of CK.
Addresses are registered at every rising edge of CK and every rising edge of CK.
GDDR5 replaces the pulsed strobes (WDQS & RDQS) used in previous DRAMs such as GDDR4 with a free running differential
forwarded clock (WCK/WCK) with both input and output data registered and driven respectively at both edges of the forwarded
WCK.
Read and write accesses to the GDDR5 SGRAM are burst oriented; accesses start at a selected location and continue for a
total of eight data words. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident with the ACTIVE command and the next rising CK edge are used to
select the bank and the row to be accessed. The address bits registered coincident with the READ or WRITE command and
the next rising CK edge are used to select the bank and the column location for the burst access.
Rev. 1.10, 2008-12
05272008-QT8C-2TYT
4
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