Ordering number:ENN1542
CMOS IC
LC3101
128K-Bit CMOS Mask ROM
Overview
The LC 3101 is a 128k-bit CMOS mask ROM that con-
tains an interface connectable direct to the speech synthe-
sizer IC LC8100. With one piece of this mask ROM, ap-
proximately 100 seconds of speech synthesis can be at-
tained. Since it also contains an interface connectable di-
rect to an EPROM, speech synthesis can be attained by
using this mask ROM and an EPROM jointly.
A selection of 8-bit, 4-bit, or single-bit output data is al-
lowed by means of external control. This mask ROM is
also suited for use in applications other than speech syn-
thesis.
Package Dimensions
unit:mm
3014A-DIP42
[LC3101]
42
22
15.24
13.8
1
53.2
21
1.2
2.54
0.5
1.2
• ROM capacity : 128K bits
• Access time : 25.6µs typ (for operation at 200kHz typ).
• Cycle time : 30.6µs typ (for operation at 200kHz typ).
• Funciton
(1) Contains an interface to an EPROM.
(2) Contains an interface to the LC8100 (sepeech
synthesizer IC).
(3) Possible to select the bit length of output data.
8-bit data
4-bit data
Single-bit data
• Low power dissipation : CMOS
• Current drain :
2mA max (at operating mode).
1µA max (at nonoperating mode).
• Single +5V power supply.
+2.7 to 6.0V (supply voltage range).
• Package : DIP24
SANYO : DIP42
unit:mm
3025B-DIP42S
[LC3101]
42
22
15.24
13.8
0.51min
Features
4.25
4.1 5.1max
1
37.9
21
0.51min 4.25
3.8 5.1max
0.95
0.48
1.78
1.15
SANYO : DIP42S
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges,or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
73101TN (KT)/7024KI, TS No.1542–1/14
0.25
0.25
LC3101
Pin Assignment
Equivalent Circuit Block Diagram
A0 to A3 :
18-bit address setting pins
ASTRB :
A0 to A3 strobe pin
DREQ :
ROM data request pin
DOUT :
ROM data serial output pin
CT :
Basic operation clock input pin
D0 to D7 :
8-bit input/output pins
MODE :
DREQ pin input pulse count control pin
DSEL :
Output bit length select pin
CE :
Power-down control pin
EA0 to EA17 : 18-bit address output pins
Description of Operation of Internal Block
• ASTRB COUNTER :
Block which internally sets address information applied in 5 steps from A0 to A3
pins.
• 18bit ADDRESS COUNTER : Address counter organized with 18 bits.
• READ PULSE COUNTER :
Block which generates signal to operate address decoder, data selector.
• CHIP SELECT DECODER :
Makes chip select signal with 2
14
to 2
17
bits or 18-bit address.
• 128kbit ROM MATRIX :
ROM matrix cell organized with 128K bits.
• PARALLEL TO SERIAL :
Shift register which serially outputs 8-bit parallel data to DOUT pin.
• I/O PORT :
Selects input/output at D0 to D7 pins.
No.1542–2/14
LC3101
Pin Description
Pin No.
34
35
36
37
38
Pin Name
ASTRB
DREQ
DOUT
CT
CE
Input/output
Input
Input
Output
Input
Input
Function
Pin for inputting strobe signal which causes data A0 to A3 to be latched at address
setting mode.
ROM data request signal input pin.
Pin for outputting ROM data serially. When used in conjunction with the LC8100, this pin
is connected to DIN pin of the LC8100.
Pin for inputting basic operation clock of ROM inside. When used in conjunction with the
LC8100, this pin is connected to CT pin of the LC8100.
Pin for controlling initialization of IC inside immediately after application of power and
internal operation stop (power-down). For performing synthesization or ROM data read-
out, set CE to 'L'.
Connected to 0V of power supply.
Connected to + side of power supply.
Always set to VSS.
Pin for controlling number of input pulses at DREQ pin. When ROM data read-out is
performed serially in a single bit, set MODE to 'L'. When ROM data read-out is
performed in 8 bits or 4 bits, set MODE to 'H'.
Used when ROM data read-out is performed in 4 bits. When DSEL is set to 'H', 2
4
to 2
7
bits are outputted to D0 D3 pins.
Pins for outputting ROM data in 8 bits and inputting data in 8 bits.
6
28
29
7
VSS
VDD
00/01
MODE
–
–
Input
Input
8
9
10
12
13
14
15
16
17
27
30
31
32
33
1
2
3
4
5
18
19
20
21
22
23
24
25
26
39
40
41
42
DSEL
D0
D1
D2
D3
D4
D5
D6
D7
MEP/EVA
A3
A2
A1
A0
EA0
EA1
EA2
EA3
EA4
EA5
EA6
EA7
EA8
EA9
EA10
EA11
EA12
EA13
EA14
EA15
EA16
EA17
Input
Input/output
Input
Input
Open or connected to VDD.
Pins for setting 18-bit address. At address setting mode, address information is inputted
by 4 bits from high-order bit downward in 5 steps.
Output
18-bit address output pins.
No.1542–3/14
LC3101
How to use the mask ROM and an EPROM jointly
The mask ROM and an external EPROM can be used jointly. Two selections of operation mode shown below are
available by high-order 4 bits (EA14 to EA17) of 18-bit address.
Operation Mode Pins
(1)
(2)
D0 to D7
Output
Input
The mask ROM contents are delivered at pins D0 to D7 and DOUT.
The EPROM output contents are read in from pins D0 to D7 and are delivered at pin DOUT.
How to select the operation mode
The LC3101 contains a 4-bit chip select decoder (user option : Refer to “User mask”). Coincidence or uncoincidence
with high-order 4 bits (EA14 to EA17) of 18-bit address is detected to select the operation mode.
Operation Mode
(1)
(2)
4bits of Chip Select Decoder
Coincidence with EA14 to EA17
Operation of LC3101
Pins D0 to D7 : Output mode
Mask ROM read enable mode
Uncoincidence with EA14 to EA17 Pins D0 to D7 : Input mode
Mask ROM read inhibit mode
Fig.1 shows the schematic diagram of the control section related to these operation modes. Fig. 2 shows the assign-
ment of 256K-byte (128k bits
×
16) that can be specified by 18-bit address.
Fig. 1 Schematic Diagram of Control Section
Fig. 2 Address Space Assignement
No.1542–4/14
LC3101
ROM Data Readout Procedure
The following flowchart shows the outline of readout procedure. (1) to (7) give a more detailed description.
(1) Initialization of internal mode
There are 4 counter blocks (ASTRB counter, 18-bit ADDRESS counter, READ PULSE counter, DREQ counter)
inside the LC3101. Since initialization is required immediately after application of power, apply one ‘H’ level
pulse to CE pin. When CE is set to ‘L’ level, the power-down mode is released (refer to (7) ) and it is possible to
start readout any time.
(2) Setting of bit length of readout data
For the bit length of ROM data output, a selection of 3 lengths is allowed : 8 bits, 4 bits, and a single bit. For
controlling this selection, MODE, DSEL pins are used. The following Table shows 3 types of pin setting.
MODE
'L'
DSEL
'L'
'H'
Single-bit length
(speech synthesis)
–
8-bit or 4-bit length or
4-bit length (Note)
4-bit length (Note)
'H'
(Note) When DSEL is set to ‘L’, 2
0
to 2
3
bits are outputted at D0 to D3 pins.
When DSEL is set to ‘H’, 2
4
to 2
7
bits are outputted at D0 to D3 pins.
No.1542–5/14
嵌入式系统
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