CY28RS680
Clock Generator for ATI
®
RS5XX/6XX Chipsets
Features
• Supports AMD
®
CPU
• Selectable CPU frequencies
• 200 MHz differential CPU clock pairs (25% over/ 50%
under clocked)
• 100 MHz differential ATI Graphics clocks (100%
over/10% under clocked)
• 100 MHz differential SRC clocks (10% over/under
clocked)
• 48 MHz USB clock
• 66 MHz HyperTransport™ clock
• I
2
C support with readback capabilities
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V power supply
•
64-pin TSSOP packages
CPU
x2
SRC
x8
HTT66
x1
ATIG
X4
REF
x3
USB_48
x2
Block Diagram
XIN
XOUT
14.318MHz
Crystal
VDD
REF[2:0]
IREF
VDD_CPU
CPUT[0:1]
CPUC[0:1]
VDD_HTT
HTT66
Pin Configuration
VSS_REF
VDD_REF
XIN
XOUT
VDD48
USB48_0
USB48_1
VSS48
SCLK
SDATA
RESET_IN#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
REF0
REF1
REF2
NC
VDD_HTT
HTT66
VSS_HTT
CLKREQA#
AMD_CPUT0
AMD_CPUC0
VDD_CPU
VSS_CPU
AMD_CPUT1
AMD_CPUC1
VDDA
VSSA
VSSSRC
SRCT0
SRCC0
VSS_SRC
VDD_SRC
SRCT1
SRCC1
ATIGT0
ATIGC0
VDD_ATIG
VSS_ATIG
ATIGT1
ATIGC1
ATIGT2
ATIGC2
CLKREQC#
PLL Reference
CPU
PLL
CLKREQ#[A:C]
Divider
VSS_SRC
SRCT6
SRCC6
CY28RS680
ATIG
PLL
Divider
VDD_SRC_IO
ATIGT[0:3]
ATIGC[0:3]
SRCT7
SRCC7
VDD_SRC
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SRC
PLL
Divider
VDD_SRC_IO
SRCT[0:7]
SRCC[0:7]
SRCT5
SRCC5
SRCT4_SATAT
SRCC4_SATAC
VSS_SRC
VDD_SRC
SRCT3
Fixed
PLL
RESET_IN#
SDATA
SCLK
I2C
Logic
Divider
VDD48
48M[0:1]
SRCC3
SRCT2
SRCC2
VDD_SRC
VSS_SRC
ATIGT3
ATIGC3
CLKREQB#
Rev 1.0, March 28, 2007
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
Page 1 of 20
www.SpectraLinear.com
CY28RS680
Pin Descriptions
Pin No.
1
2
3
4
5
6, 7
8
9
10
11
Name
VSS_REF
VDD_REF
XIN
XOUT
VDD_48
USB_48 [1:0]
VSS_48
SCLK
SDATA
RESET_IN#
Type
PWR
PWR
I
O
PWR
GND
I,PU
GND for REF, XTAL
3.3V power supply for REF, XTAL
14.318 MHz Crystal Input
14.318 MHz Crystal Output
3.3V power supply for USB outputs
Ground for USB outputs
SMBus-compatible SCLOCK.This pin has an internal pull up, but is tri-stated in
power down.
Description
O, SE 48 MHz clock output. Intel
®
Type-3A buffer.
I/O,PU SMBus-compatible SDATA.This pin has an internal pull up, but is tri-stated in
power down.
I
3.3V LVTTL Input (Negative Edge Triggered)
When this pin is asserted LOW, all PLLs will transition to a safe default frequency.
This may be the POR defaults or a safe value stored in SMBUS registers.
12, 13
14
15
16, 17, 18,
19, 20, 21
22
23
24, 25, 26,
27
28
29
30,31
32, 33
SRCT/C[7]
VDD_SRC
VSS_SRC
SRCT/C[6:4]
VSS_SRC
VDD_SRC
SRCT/C[3:2]
VDD_SRC
VSS_SRC
ATIGT/C3
CLKREQ#[B:C]
O, DIF 100 MHz differential serial reference clock. Intel Type-SR buffer.
(10% overclocking support through SMBUS)
PWR
GND
3.3V power supply for SRC outputs
Ground for SRC outputs
O, DIF 100 MHz differential serial reference clock. Intel Type-SR buffer.
(10% overclocking support through SMBUS)
GND
PWR
Ground for SRC outputs
3.3V power supply for SRC outputs
O, DIF 100 MHz differential serial reference clock. Intel Type-SR buffer.
(10% overclocking support through SMBUS)
PWR
GND
3.3V power supply for SRC outputs
Ground for SRC outputs
O, DIF Differential Selectable serial reference clock. Intel Type-SR buffer.
Includes 50% overclock support through SMBUS
I, SE, Output Enable control for SRCT/C. Output enable control required by Minicard
PU specification. This pin has an internal pull up. 0 = Selected SRC output is enabled.
1 = Selected SRC output is disabled
O, DIF Differential Selectable serial reference clock. Intel Type-SR buffer.
Includes 50% overclock support through SMBUS
GND
PWR
Ground for ATIG outputs
3.3V power supply for ATIG outputs
34, 35, 36, 37
38
39
40, 41
42, 43
44
45
46,47
48
49
50
ATIGT/C[2:1]
VSS_ATIG
VDD_ATIG
ATIGT/C0
SRCT/C1
VDD_SRC
VSS_SRC
SRCT/C0
VSS_SRC
VSSA
VDDA
O, DIF Differential Selectable serial reference clock. Intel Type-SR buffer.
Includes 50% overclock support through SMBUS
O, DIF 100 MHz differential serial reference clock. Intel Type-SR buffer.
(10% overclocking support through SMBUS)
PWR
GND
3.3V power supply for SRC outputs
Ground for SRC outputs
O, DIF 100 MHz differential serial reference clock. Intel Type-SR buffer.
(10% overclocking support through SMBUS)
GND
GND
PWR
Ground for SRC outputs
Analog Ground
3.3V Analog Power for PLLs
Rev 1.0, March 28, 2007
Page 2 of 20
CY28RS680
Pin Descriptions
(continued)
Pin No.
51, 52, 55, 56
53
54
57
Name
CPUT/C[1:0]
VSS_CPU
VDD_CPU
CLKREQ#A
Type
O, DIF Differential CPU clock output.
Intel Type-SR buffer
GND
PWR
Ground for CPU outputs
3.3V power supply for CPU outputs
Description
I, SE, Output Enable control for SRCT/C. Output enable control required by Minicard
PU specification. This pin has an internal pull up.
0 = Selected SRC output is enabled. 1 = Selected SRC output is disabled.
PWR
PWR
I
Ground for HyperTransport outputs
3.3V power supply for HyperTransport outputs
No Connect
O, SE 66 MHz clock output. Intel Type-5 buffer.
58
59
60
61
62, 63, 64
VSS_HTT
HTT66
VDD_HTT
NC
REF[2:0]
O, SE 14.318 MHz REF clock output. Intel Type-5 buffer.
Rev 1.0, March 28, 2007
Page 3 of 20
CY28RS680
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initialize to their default setting upon power up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in
Table 1.
The block write and block read protocol is outlined in
Table 2
while
Table 3
outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
.
Table 1. Command Code Definition
Bit
7
(6:5)
(4:0)
Chip select address, set to ‘00’ to access device
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '00000'
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
36:29
37
45:38
46
....
....
....
....
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Byte Count – 8 bits
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data byte 2 – 8 bits
Acknowledge from slave
Data Byte /Slave Acknowledges
Data Byte N – 8 bits
Acknowledge from slave
Stop
Description
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
38
46:39
47
55:48
56
....
....
....
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read = 1
Acknowledge from slave
Byte Count from slave – 8 bits
Acknowledge
Data byte 1 from slave – 8 bits
Acknowledge
Data byte 2 from slave – 8 bits
Acknowledge
Data bytes from slave / Acknowledge
Data Byte N from slave – 8 bits
NOT Acknowledge
Block Read Protocol
Description
Rev 1.0, March 28, 2007
Page 4 of 20
CY28RS680
Table 3. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
29
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Data byte – 8 bits
Acknowledge from slave
Stop
Description
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
38
39
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Repeated start
Slave address – 7 bits
Read
Acknowledge from slave
Data from slave – 8 bits
NOT Acknowledge
Stop
Byte Read Protocol
Description
Control Registers
Byte 0: Output Enable Register 0
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Name
SRC[T/C]7
SRC[T/C]6
SRC[T/C]5
SRC[T/C]4
SRC[T/C]3
SRC[T/C]2
SRC[T/C]1
SRC [T/C]0
SRC[T/C]7 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]6 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]5 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]4 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]3 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]2 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
Description
Byte 1: Output Enable Register 1
Bit
7
6
5
4
3
2
@Pup
1
1
1
1
1
1
Name
Reserved
Reserved
ATIG[T/C]3
ATIG[T/C]2
ATIG[T/C]1
ATIG[T/C]0
Reserved
Reserved
ATIG[T/C]3 Output Enable
0 = Disable (Hi-Z), 1 = Enable
ATIG[T/C]2 Output Enable
0 = Disable (Hi-Z), 1 = Enable
ATIG[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
ATIG[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
Description
Rev 1.0, March 28, 2007
Page 5 of 20
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