IR3522
DATA SHEET
XPHASE3
TM
DDR & VTT CONTROL IC
DESCRIPTION
The IR3522 Control IC combined with IR3506
xPHASE3
TM
Phase ICs implements a full featured DDR3
power solution. The IR3522 provides control functions for both the VTT (single phase) and VDDR
(multiphase) power rails which can interfaces with any number of IR3506 ICs each driving and monitoring
TM
a single phase to power any number of DDR3 DIMMs. The
xPHASE3
architecture delivers a power
supply that is smaller, more flexible, and easier to design while providing higher efficiency than
conventional approaches.
FEATURES
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I
2
C interface programs 1.025V< VREF1<1.612V, the VDD output voltage reference
I
2
C also programs the VTT tracking ratio ± 25 %, and provides digital ON/OFF control
Four different I
2
C addresses are selectible using 2 ADDR pins
Four different VREF1 voltages are selectible using 2 VID pins if I
2
C communication is not available
VTT tracking defaults to ½ the VDD Remote Sense Amp output voltage
Power Good output driven by an external bias input
VDD to VTT overvoltage protection
Soft-Stop turn-off to ensure VDDR and Vtt tracking
Fault activated Crowbar pin to drive external NMOS devices for external output voltage protection
Pin programmable slew rate of I
2
C programmed VREF1 voltage transitions
0.5% overall VDD system set point accuracy
Remote sense amplifiers provide differential sensing and requires less than 50uA bias current
Pin programmable per phase switching frequency of 250kHz to 1.5MHz
Complete protection including over-current, over-voltage, open remote sense, and open control
APPLICATION CIRCUIT
12V
VCCL
CVCCL
12V
VCCL
To Converters
To Phase IC
VCCL & GATE
DRIVE BIAS
Phase Clock Input to
Last Phase IC of VDD
2 wire Digital
Daisy Chain Bus
to Phase ICs
PGOOD
PHSIN
PHSOUT
28
30
29
26
32
31
27
25
CLKOUT
SCL
SDA
VI D1
VI D0
VCCL
SCL
RPGBIAS
1
2
SD A
PGBIAS
EN ABLE
IIN 2
AD DR1
AD DR2
OCSET2
VOSEN2+
VOSEN1+
VOSEN2-
VOSEN1-
EAOUT2
VOUT2
FB2
PHSOUT
CLKOUT
PGOOD
PHSIN
LGND
ROSC
24
23
22
21
20
RVR EF
19
18
17
ROCSET1
CSS/DEL
CVREF
ROSC
ENABLE
3
4
5
6
ROCSET2
7
8
IR3522
CONTROL
IC
CROWBAR
II N1
SS/ DEL1
VREF1
OCSET1
EAOUT1
VOUT1
FB1
CROWBAR
Drives NMOS crowbar
devices at VTT and
VDDR rails
10
11
12
13
14
15
RCP2
CCP21
RFB22
R FB21
CFB2
CFB1
16
9
RFB12
R CP1
CCP11
ISHARE1
EAOUT1
VREF1
EAOUT2
ISHARE2
CCP22
RFB11
CCP12
5 Wire Analog
Phase IC
Control Bus
To Vtt
Remote
Sense
VTT SENSE +
VTT SENSE -
DDR SENSE +
DDR SENSE -
To VDD
Remote
Sense
Figure 1
– IR3522 Application Circuit
Page 1
V3.01
IR3522
ORDERING INFORMATION
Device
IR3522MTRPBF
* IR3522MPBF
* Samples only
Package
32 Lead MLPQ (5 x 5 mm body)
32 Lead MLPQ (5 x 5 mm body)
Order Quantity
3000 per reel
100 piece strips
PIN DESCRIPTION
PIN#
1
PIN SYMBOL
SDA
PIN DESCRIPTION
SDA (Serial Data) is a bidirectional signal that is an input and open drain output for
both master (I
2
C controller) and slave (IR3522). SDA requires a pull resistor to a
bias voltage and should not be floated.
Input to provide bias to the Power Good output transistor directly from the converter
input voltage. Enables the Power Good output to assert even if there is no bias
supplied to the VCCL pin. Internal voltage clamp protects the pin. Do not exceed
100 uA of pull-up current.
Enable input. A logic low applied to this pin puts the IC into fault mode. A logic high
on the pin resets and enables the converter. Do not float this pin as the logic state
will be undefined.
Output 2 average current input from the output 2 phase IC(s).
Digital input to program bit 1 of the 2 bit address code with internal pull-up. Connect
to LGND for logic “0”, float for logic “1”
Digital input to program bit 2 of the 2 bit address code with internal pull-up. Connect
to LGND for logic “0”, float for logic “1”
Programs the output 2 constant converter output current limit through an external
resistor tied to VREF1 and an internal current source from this pin. Over-current
protection can be disabled by over sizing the resistor value to program the threshold
higher than IIN2 pin possible signal amplitude, but no greater than 5V (do not float
this pin as improper operation will occur).
Output of the output 2 error amplifier.
Inverting input to the output 2 error amplifier.
Output 2 remote sense amplifier output.
Output 2 remote sense amplifier input. Connect to output at the load.
Output 2 remote sense amplifier input. Connect to ground at the load.
Output 1 remote sense amplifier input. Connect to ground at the load.
Output 1 remote sense amplifier input. Connect to output at the load.
Output 1 remote sense amplifier output. Provides reference to Error Amp2.
Inverting input to the output 1 error amplifier.
Output of the output 1 error amplifier.
Programs the output 1 constant converter output current limit through an external
resistor tied to VREF1 and an internal current source from this pin. Over-current
protection can be disabled by over sizing the resistor value to program the threshold
higher than IIN2 pin possible signal amplitude, but no greater than 5V (do not float
this pin as improper operation will occur).
Reference voltage programmed by the I
2
C inputs and error amplifier non-inverting
input. Connect an external RC network to LGND to program dynamic VID slew rate
and provide compensation for the internal buffer amplifier.
Connect an external capacitor to LGND to program startup and Fault delay timing
2
PGBIAS
3
ENABLE
4
5
6
7
IIN2
ADDR1
ADDR2
OCSET2
8
9
10
11
12
13
14
15
16
17
18
EAOUT2
FB2
VOUT2
VOSEN2+
VOSEN2-
VOSEN1-
VOSEN1+
VOUT1
FB1
EAOUT1
OCSET1
19
VREF1
20
SS/DEL1
Page 2
V3.01
IR3522
PIN#
21
22
23
PIN SYMBOL
IIN1
CROWBAR
ROSC
PIN DESCRIPTION
Output 1 average current input from the output 1 phase IC(s). This pin is also used
to initialize Diode Emulation Mode in the phase IC(s).
Drives NMOS crowbar devices at VTT and VDDR rails.
Connect a resistor to LGND to program oscillator frequency and OCSET1, OCSET2,
and VREF bias currents. Oscillator frequency equals switching frequency per phase.
The pin voltage is 0.6V during normal operation.
Local Ground for internal circuitry and IC substrate connection.
Clock output at switching frequency multiplied by phase number. Connect to CLKIN
pins of phase ICs.
Phase clock output at switching frequency per phase. Connect to PHSIN pin of the
first phase IC.
Feedback input of phase clock. Connect to PHSOUT pin of the last phase IC.
Output of the voltage regulator, and power input for clock oscillator circuitry. Connect
a decoupling capacitor to LGND.
Digital input to program one of four power-up VREF1 VDD reference values.
Connect to LGND for logic “0”, float for logic “1”
Digital input to program one of four power-up VREF1 VDD reference values.
Connect to LGND for logic “0”, float for logic “1”
Open collector output that drives low during startup and under any external fault
condition. The Power Good function also monitors output voltages and this pin will
drive low if any of the voltage planes are outside of the specified limits. Connect
external pull-up.
SCL (Serial Clock) is an open drain output of the I
2
C controller and input to IR3522.
This pin requires an external bias voltage and should not be floated.
24
25
26
27
28
29
30
31
LGND
CLKOUT
PHSOUT
PHSIN
VCCL
VID0
VID1
PGOOD
32
SCL
Page 3
V3.01
IR3522
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed below may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications are not implied. All voltages are absolute voltages referenced to the
LGND pin.
Operating Junction Temperature……………..0 to 150 C
Storage Temperature Range………………….-65
o
C to 150
o
C
ESD Rating………………………………………HBM Class 1C JEDEC Standard
MSL Rating………………………………………2
Reflow Temperature…………………………….260
o
C
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PIN NAME
SDA
PGBIAS
ENABLE
IIN2
ADDR1
ADDR2
OCSET2
EAOUT2
FB2
VOUT2
VOSEN2+
VOSEN2-
VOSEN1-
VOSEN1+
VOUT1
FB1
EAOUT1
OCSET1
VREF1
SS/DEL1
IIN1
CROWBAR
ROSC
LGND
CLKOUT
PHSOUT
PHSIN
VCCL
VID0
VID1
PGOOD
SCL
V
MAX
8V
8V
3.5V
8V
3.5V
3.5V
8V
8V
8V
8V
8V
1.0V
1.0V
8V
8V
8V
8V
8V
3.5V
8V
V(VCCL) + 1.1 V
8V
8V
n/a
8V
8V
8V
8V
8V
8V
VCCL + 0.3V
8V
V
MIN
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.5V
-0.5V
-0.5V
-0.5V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
n/a
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
I
SOURCE
1mA
1mA
1mA
5mA
1mA
1mA
1mA
25mA
1mA
5mA
5mA
5mA
5mA
5mA
5mA
1mA
25mA
1mA
1mA
1mA
5mA
35mA
1mA
20mA
100mA
10mA
1mA
1mA
1mA
1mA
1mA
1mA
I
SINK
10mA
1mA
1mA
1mA
1mA
1mA
1mA
10mA
1mA
25mA
1mA
1mA
1mA
1mA
25mA
1mA
10mA
1mA
1mA
1mA
1mA
1mA
1mA
1mA
100mA
10mA
1mA
20mA
1mA
1mA
20mA
1mA
o
Page 4
V3.01
IR3522
RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN
4.75V
≤
VCCL
≤
7.5V, -0.3V
≤
VOSEN-x
≤
0.3V, 0
o
C
≤
T
J
≤
100
o
C, 7.75 k
≤
R
OSC
≤
50 k , C
SS/DEL1
= 0.1uF
ELECTRICAL CHARACTERISTICS
The electrical characteristics table list the spread of critical values that are guaranteed to be within the recommended
C.
operating conditions (unless otherwise specified). Typical values represent the median values, which are related to 25°
PARAMETER
SVID Interface
SCL & SDA Input Thresholds
TEST CONDITION
Threshold Increasing
Threshold Decreasing
Threshold Hysteresis
0V
≤
V(x)
≤
3.5V, SDA not asserted
I(SDA)= 3mA
0.7 x VDD to 0.3 x VDD, 1.425V
≤
VDD
≤
1.9V, 10 pF
≤
Cb
≤
400 pF,
Cb=capacitance of one bus line (Note 1)
Note 1
Pull-up to 3.3 V typical
MIN
1.265
1.04
150
-5
20+ 0.1
xCb(pF)
85
50
1.38
3.1
-10%
0.57
TYP
1.325
1.1
225
0
20
MAX
1.385
1.16
300
5
300
250
UNIT
V
V
mV
uA
mV
ns
Bias Current
SDA Low Voltage
SDA Output Fall Time
Pulse width of spikes suppressed
by the input filter
ADDRx Internal Pull-up
ADDRx Threshold Voltage
ADDRx Float Voltage
260
100
1.65
3.3
See
Figure 2
0.600
550
250
1.94
3.5
+10%
0.630
1
1
1
1
70
9.0
3
ns
k
V
V
kHz
V
V
V
V
V
%
MHz
mV
Oscillator
PHSOUT Frequency
ROSC Voltage
CLKOUT High Voltage
CLKOUT Low Voltage
PHSOUT High Voltage
PHSOUT Low Voltage
PHSIN Threshold Voltage
Unity Gain Bandwidth
Input Offset Voltage
I(CLKOUT)= -10 mA, measure V(VCCL) –
V(CLKOUT).
I(CLKOUT)= 10 mA
I(PHSOUT)= -1 mA, measure V(VCCL) –
V(PHSOUT)
I(PHSOUT)= 1 mA
Compare to V(VCCL)
Note 1
1.025 V
≤
V(VOSEN1+) - V(VOSEN1-)
≤
1.6125 V, 385mV
≤
V(VOSEN2+) -
V(VOSEN2-)
≤
1.021 V, Note 2
1.025 V
≤
V(VOSEN1+) - V(VOSEN1-)
≤
1.6125 V, 385mV
≤
V(VOSEN2+) -
V(VOSEN2-)
≤
1.021 V
1.025 V
≤
V(VOSEN1+) - V(VOSEN1-)
≤
1.6125 V, 385mV
≤
V(VOSEN2+) -
V(VOSEN2-)
≤
1.021 V
1.025 V
≤
V(VOSEN1+) - V(VOSEN1-)
≤
1.6125 V, 385mV
≤
V(VOSEN2+) -
V(VOSEN2-)
≤
1.021 V
Note 1.
1.025 V
≤
V(VOSEN1+) - V(VOSEN1-)
≤
1.6125 V, 385mV
≤
V(VOSEN2+) -
V(VOSEN2-)
≤
1.021 V
1.025 V
≤
V(VOSEN1+) - V(VOSEN1-)
≤
1.6125 V, 385mV
≤
V(VOSEN2+) -
V(VOSEN2-)
≤
1.021 V, All VID Codes
V(VCCL) =7V
V(VCCL) – V(VOUTx)
30
3.0
-3
50
6.4
0
Remote Sense Differential Amplifiers
Source Current
3
7
15
mA
Sink Current
300
450
650
uA
Slew Rate
2
4
8
V/us
VOSEN+ Bias Current
30
50
uA
VOSEN- Bias Current
30
50
uA
Low Voltage
High Voltage
1.2
1.8
40
2.3
mV
V
Page 5
V3.01
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