Contents
Features ...........................................................1
Pin Assignment ................................................1
Block Diagram..................................................1
Instruction Set ..................................................2
Absolute Maximum Ratings .............................2
Recommended Operating Conditions..............2
Pin Capacitance ...............................................3
DC Electrical Characteristics............................3
AC Electrical Characteristics............................4
Operation .........................................................5
Three-wire Interface
•DI-DO
Direct Connecting...........................8
Ordering Information ........................................9
Characteristics ...............................................10
Dimensions ....................................................14
DI
SC
ON
TI
NU
ED
PR
OD
UC
T
Rewriting Times ...............................................2
Rev.1.11
CMOS 2K/4K-bit SERIAL E
2
PROM
S-29255A/29355A
2
The S-29255A (2K-bit) and S-29355A (4K-bit) are E PROMs
characterized by a wide operating voltage range and low power
consumption. The organization is 128-word×16-bit and 256-word×16-
bit, respectively. They are easily interfaced with a serial port because
the instruction is composed of eight-bit units. Also, through the RESET
pin, erroneous writing at power on/off can be avoided.
•
S-29255A :
S-29355A :
2K-bit, instruction code conforming to M6M80021
4K-bit, instruction code conforming to M6M80041
•
Low power consumption Operating: 2.0 mA max.
Standby: 1.0
µA
max.
•
Wide operating voltage range
Write: 2.7 to 6.5 V
Read: 1.8 to 6.5 V
T
T
Package
O
8-pin DIP
O
8-pin SOP
(PKG drawing code : DP008-A)
(PKG drawing code : FE008-A)
Pin Assignment
8-pin DIP
Top view
CS
SK
DI
DO
V
CC
RDY/BUSY
RESET
GND
ED
TI
NU
8-pin SOP
Top view
RDY/BUSY
V
CC
RESET
GND
DO
DI
CS
SK
PR
CS
SK
DI
DO
V
CC
GND
RDY/BUSY
RESET
Chip select
Serial clock
Serial data input
Serial data output
Power supply voltage
Ground
Ready output/Busy output
Reset input
L : Stable Status
H : Reset write circuit
(Memory protection)
Figure 1
Memory array
Address
decoder
Data register
Output buffer
DO
T
Block Diagram
DI
RESET
SC
DI
CS
Clock
generator
ON
Write
protection
OD
UC
T
•
•
•
•
•
•
T
Features
Easy interface with serial port
Memory protection by RESET pin
Rewritings: 10
5
times/word
Data retention: 10 years
Operating temperature: -40
°C
to+85
°C
Package: 8-pin DIP/SOP, bare chip
Mode decode logic
RDY/BUSY
Figure 2
V
CC
GND
SK
Seiko Instruments Inc.
1
CMOS 2K/4K-bit SERIAL E
2
PROM
S-29255A/29355A
n
Instruction Set
Table 1
Instruction
Op code
Address
S-29255A
READ
(Read data)
PROGRAM
(Program)
WRAL
(Write all )*
ERAL
(Erase all )*
EWEN
(Program enable)
EWDS
(Program disable)
Status output
Busy flag
Write permission
ECC flag
10101000
10100100
10100001
10100010
10100011
10100000
10101001
A
0
to A
6
0
A
0
to A
6
0
A
0
to A
6
0
xxxxxxxx
xxxxxxxx
xxxxxxxx
00xxxxxx
10xxxxxx
01xxxxxx
S-29355A
A
0
to A
7
A
0
to A
7
A
0
to A
7
xxxxxxxx
xxxxxxxx
xxxxxxxx
00xxxxxx
10xxxxxx
01xxxxxx
D
0
to D
15
D
0
to D
15
D
0
to D
15
0 : BUSY 1 : READY
0 : Permission 1 : Inhibit
"
0
"
is always output**
Data
x : Doesn
’
t matter
* : ERAL and WRAL are options. Normally these can not be used.
** : S-29255A/29355A doesn't have redundant memory.
n
Absolute Maximum Ratings
Table 2
Parameter
Power supply voltage
Input voltage
Output voltage
Storage temperature under bias
Storage temperature
Symbol
V
CC
V
IN
V
OUT
T
bias
T
stg
PR
n
Recommended Operating Conditions
Parameter
Power supply voltage
High level input voltage
TI
NU
Symbol
V
CC
V
IH
ED
Table 3
Conditions
-0.3 to +7.0
-0.3 to V
CC
+0.3
-0.3 to V
CC
-50 to+95
-65 to+150
OD
UC
T
Ratings
Unit
V
V
V
°C
°C
Min.
1.8
2.7
0.8×V
CC
0.7×V
CC
0.8×V
CC
0.0
0.0
0.0
-40
Typ.
(Ta=-40°C to 85°C)
Max.
Unit
times/word
Max.
6.5
6.5
V
CC
V
CC
V
CC
0.2×V
CC
0.3×V
CC
0.2×V
CC
+85
Unit
V
V
V
V
V
V
V
V
°C
Read
Write
ON
V
IL
T
opr
N
W
Low level input voltage
Operating temperature
n
Rewriting Times
DI
Parameter
Rewriting times
Symbol
SC
CS, SK
DI, RESET
V
CC
=1.8 to 2.7V
CS, SK
V
CC
=2.7
to 6.5V
DI, RESET
V
CC
=1.8 to 2.7V
V
CC
=2.7
to 6.5V
Table 4
Min.
10
5
Typ.
2
Seiko Instruments Inc.
CMOS 2K/4K-bit SERIAL E
2
PROM
S-29255A/29355A
n
Pin Capacitance
Table 5
(Ta=25°C, f=1.0 MHz, V
CC
=5 V)
Parameter
Input capacitance
Output capacitance
Symbol
C
IN
C
OUT
Conditions
V
IN
=0 V
V
OUT
=0 V
Min.
Typ.
Max.
8
10
Unit
pF
pF
n
DC Electrical Characteristics
Table 6
(Ta=-40°C to 85°C)
Parameter
Smbl
Conditions
Read/write operations
V
CC
=5.0 V±10 %
Min.
Current consumption
(READ)
Current consumption
(PROGRAM)
I
CC1
I
CC2
DO unloaded
DO unloaded
Typ.
OD
UC
T
V
CC
=3.0 V±10 %
Typ.
Max.
2.0
5.0
Min.
Max.
1.0
2.0
V
CC
=2.7 to 6.5 V
Typ.
0.1
0.1
Max.
1.0
1.0
1.0
0.1
--
Max.
1.0
1.0
1.0
0.1
Min.
0.45
V
CC
-0.7
1.5
V
CC
×0.1
Read operation
V
CC
=1.8 to 2.7 V
Typ.
Max.
0.5
Unit
Min.
mA
mA
PR
Table 7
Parameter
Smbl
Conditions
(Ta=-40°C to 85°C)
Read operation
V
CC
=1.8 to 2.7 V
Min.
V
CC
-0.3
Typ.
0.1
0.1
Max.
1.0
1.0
1.0
0.1
µA
µA
µA
V
V
V
Unit
Read/write operations
V
CC
=5.0 V±10 %
Standby current
consumption
Input leakage current
Output leakage
current
Low level output
voltage
High level output
voltage
I
SB
I
LI
I
LO
V
OL
Input: V
CC
or GND
V
IN
=GND to V
CC
V
OUT
=GND to V
CC
TI
NU
CMOS I
OL
=100
µA
V
OH
ON
TTL I
OL
=2.1 mA
CMOS
V
CC
=2.7 to 6.5 V:
I
OH
=-100
µA
V
CC
=1.8 to 2.7 V:
I
OH
=-10
µA
TTL I
OH
=-400
µA
ED
0.1
0.1
V
CC
-0.7
Min.
Typ.
SC
Write enable latch
data hold voltage
Schmitt width
V
DH
2.4
1.5
V
CC
×0.1
1.5
0.05
V
V
V
V
WD
CS, SK
DI
Seiko Instruments Inc.
3
CMOS 2K/4K-bit SERIAL E
2
PROM
S-29255A/29355A
n
AC Electrical Characteristics
Table 8 Measuring conditions
Input pulse voltage
0.1×V
CC
to 0.9×V
CC
Output reference voltage
0.5×V
CC
Output load
100 pF
Table 9
(Ta=-40°C to 85°C)
Parameter
Symbol
Read / Write operations
V
CC
=5.0 V±10 %
CS setup time
CS hold time
CS setup time (CPU)
CS hold time (CPU)
CS deselect time
Data setup time
Data hold time
1 data output delay
0 data output delay
Clock frequency
Clock pulse width
Output disable time
Program time
t
CSS
t
CSH
t
CSS(CPU)
t
CSH(CPU)
t
CDS
t
DS
t
DH
t
PD1
t
PD0
f
SK
t
SKH,
t
SKL
t
HZ
t
PR
Min.
0.2
0.2
0.2
0.2
0.4
0.2
0.2
0.0
0.25
0
Typ.
50
4.0
Max.
0.4
0.4
2.0
150
10
V
CC
=2.7 to 6.5 V
Min.
0.4
0.4
0.4
0.4
1.0
0.4
0.4
0.0
0.5
0
Typ. Max.
1.0
1.0
1.0
500 1000
4.0
10
Read operation
V
CC
=1.8 to 2.7 V
Min.
1.0
1.0
1.0
1.0
2.0
0.8
0.8
0.0
2.5
Typ.
Max.
µs
µs
µs
µs
µs
µs
µs
2.0
µs
2.0
µs
0.2 MHz
µs
ns
ms
Unit
CS
t
CSS
SK
t
DS
DI
t
DH
t
SKH
ED
t
SKL
Valid data
PR
Valid data
TI
NU
t
PD0
DO
ON
Figure 3 Timing chart
CS
SC
t
CSS(CPU)
4
DI
SK
Figure 4 Timing chart of t
CSS(CPU)
and t
CSH(CPU)
when connected to CPU
Seiko Instruments Inc.
OD
UC
T
t
CSH
t
CDS
t
PD1
t
CSH(CPU)
Input data is fetched at the rise of SK.
Output data is triggered at the fall of SK.
FPGA/CPLD
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