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CY7C1380D-200BGXI

产品描述Cache SRAM, 512KX36, 3ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, BGA-119
产品类别存储    存储   
文件大小554KB,共30页
制造商Cypress(赛普拉斯)
标准
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CY7C1380D-200BGXI概述

Cache SRAM, 512KX36, 3ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, BGA-119

CY7C1380D-200BGXI规格参数

参数名称属性值
是否Rohs认证符合
厂商名称Cypress(赛普拉斯)
零件包装代码BGA
包装说明14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, BGA-119
针数119
Reach Compliance Codecompliant
ECCN代码3A991.B.2.A
最长访问时间3 ns
其他特性PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)200 MHz
I/O 类型COMMON
JESD-30 代码R-PBGA-B119
JESD-609代码e1
长度22 mm
内存密度18874368 bit
内存集成电路类型CACHE SRAM
内存宽度36
湿度敏感等级3
功能数量1
端子数量119
字数524288 words
字数代码512000
工作模式SYNCHRONOUS
最高工作温度85 °C
最低工作温度-40 °C
组织512KX36
输出特性3-STATE
封装主体材料PLASTIC/EPOXY
封装代码BGA
封装等效代码BGA119,7X17,50
封装形状RECTANGULAR
封装形式GRID ARRAY
并行/串行PARALLEL
峰值回流温度(摄氏度)260
电源2.5/3.3,3.3 V
认证状态Not Qualified
座面最大高度2.4 mm
最大待机电流0.07 A
最大压摆率0.3 mA
最大供电电压 (Vsup)3.6 V
最小供电电压 (Vsup)3.135 V
标称供电电压 (Vsup)3.3 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子面层Tin/Silver/Copper (Sn/Ag/Cu)
端子形式BALL
端子节距1.27 mm
端子位置BOTTOM
处于峰值回流温度下的最长时间20
宽度14 mm

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CY7C1380D
CY7C1382D
18-Mbit (512K x 36/1M x 18)
Pipelined SRAM
Features
• Supports bus operation up to 250 MHz
• Available speed grades are 250, 200, and 167 MHz
• Registered inputs and outputs for pipelined operation
• 3.3V core power supply
• 2.5V/3.3V I/O power supply
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
• Provide high-performance 3-1-1-1 access rate
User-selectable burst counter supporting Intel
®
Pentium
®
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Single Cycle Chip Deselect
• Available in JEDEC-standard lead-free 100-pin TQFP,
lead-free and non-lead-free 119-ball BGA and 165-ball
FBGA package
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• “ZZ” Sleep Mode Option
Functional Description
[1]
The CY7C1380D/CY7C1382D SRAM integrates 524,288 x 36
and 1,048,576 x 18 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered Clock Input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining Chip Enable (CE
1
), depth-expansion Chip
Enables (CE
2
and CE
3[2]
), Burst Control inputs (ADSC, ADSP,
and ADV), Write Enables (BW
X
, and BWE), and Global Write
(GW). Asynchronous inputs include the Output Enable (OE)
and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two or four bytes wide as
controlled by the byte write control inputs. GW when active
LOW causes all bytes to be written.
The CY7C1380D/CY7C1382D operates from a +3.3V core
power supply while all outputs may operate with either a +2.5
or +3.3V supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Selection Guide
250 MHz
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
2.6
350
70
200 MHz
3.0
300
70
167 MHz
3.4
275
70
Unit
ns
mA
mA
Notes:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
2. CE
3
, CE
2
are for TQFP and 165 FBGA package only. 119 BGA is offered only in 1 Chip Enable.
Cypress Semiconductor Corporation
Document #: 38-05543 Rev. *D
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised June 23, 2006

CY7C1380D-200BGXI相似产品对比

CY7C1380D-200BGXI CY7C1380D-250BGXI CY7C1380D-200BGI CY7C1382D-200BGI CY7C1382D-250BGXI CY7C1380D-250BGI CY7C1382D-250BGI CY7C1382D-200BGXI
描述 Cache SRAM, 512KX36, 3ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, BGA-119 Cache SRAM, 512KX36, 2.6ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, BGA-119 Cache SRAM, 512KX36, 3ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, BGA-119 Cache SRAM, 1MX18, 3ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, BGA-119 Cache SRAM, 1MX18, 2.6ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, BGA-119 Cache SRAM, 512KX36, 2.6ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, BGA-119 Cache SRAM, 1MX18, 2.6ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, BGA-119 Cache SRAM, 1MX18, 3ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, BGA-119
是否Rohs认证 符合 符合 不符合 不符合 符合 不符合 不符合 符合
零件包装代码 BGA BGA BGA BGA BGA BGA BGA BGA
包装说明 14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, BGA-119 14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, BGA-119 14 X 22 MM, 2.40 MM HEIGHT, BGA-119 14 X 22 MM, 2.40 MM HEIGHT, BGA-119 14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, BGA-119 14 X 22 MM, 2.40 MM HEIGHT, BGA-119 14 X 22 MM, 2.40 MM HEIGHT, BGA-119 14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, BGA-119
针数 119 119 119 119 119 119 119 119
Reach Compliance Code compliant compliant compliant compliant compliant compliant compliant compliant
ECCN代码 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A
最长访问时间 3 ns 2.6 ns 3 ns 3 ns 2.6 ns 2.6 ns 2.6 ns 3 ns
其他特性 PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE
最大时钟频率 (fCLK) 200 MHz 250 MHz 200 MHz 200 MHz 250 MHz 250 MHz 250 MHz 200 MHz
I/O 类型 COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON
JESD-30 代码 R-PBGA-B119 R-PBGA-B119 R-PBGA-B119 R-PBGA-B119 R-PBGA-B119 R-PBGA-B119 R-PBGA-B119 R-PBGA-B119
JESD-609代码 e1 e1 e0 e0 e1 e0 e0 e1
长度 22 mm 22 mm 22 mm 22 mm 22 mm 22 mm 22 mm 22 mm
内存密度 18874368 bit 18874368 bit 18874368 bit 18874368 bit 18874368 bit 18874368 bit 18874368 bit 18874368 bit
内存集成电路类型 CACHE SRAM CACHE SRAM CACHE SRAM CACHE SRAM CACHE SRAM CACHE SRAM CACHE SRAM CACHE SRAM
内存宽度 36 36 36 18 18 36 18 18
功能数量 1 1 1 1 1 1 1 1
端子数量 119 119 119 119 119 119 119 119
字数 524288 words 524288 words 524288 words 1048576 words 1048576 words 524288 words 1048576 words 1048576 words
字数代码 512000 512000 512000 1000000 1000000 512000 1000000 1000000
工作模式 SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
最高工作温度 85 °C 85 °C 85 °C 85 °C 85 °C 85 °C 85 °C 85 °C
最低工作温度 -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C
组织 512KX36 512KX36 512KX36 1MX18 1MX18 512KX36 1MX18 1MX18
输出特性 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 BGA BGA BGA BGA BGA BGA BGA BGA
封装等效代码 BGA119,7X17,50 BGA119,7X17,50 BGA119,7X17,50 BGA119,7X17,50 BGA119,7X17,50 BGA119,7X17,50 BGA119,7X17,50 BGA119,7X17,50
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 GRID ARRAY GRID ARRAY GRID ARRAY GRID ARRAY GRID ARRAY GRID ARRAY GRID ARRAY GRID ARRAY
并行/串行 PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL
峰值回流温度(摄氏度) 260 260 NOT SPECIFIED NOT SPECIFIED 260 NOT SPECIFIED NOT SPECIFIED 260
电源 2.5/3.3,3.3 V 2.5/3.3,3.3 V 2.5/3.3,3.3 V 2.5/3.3,3.3 V 2.5/3.3,3.3 V 2.5/3.3,3.3 V 2.5/3.3,3.3 V 2.5/3.3,3.3 V
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
座面最大高度 2.4 mm 2.4 mm 2.4 mm 2.4 mm 2.4 mm 2.4 mm 2.4 mm 2.4 mm
最大待机电流 0.07 A 0.07 A 0.07 A 0.07 A 0.07 A 0.07 A 0.07 A 0.07 A
最大压摆率 0.3 mA 0.35 mA 0.3 mA 0.3 mA 0.35 mA 0.35 mA 0.35 mA 0.3 mA
最大供电电压 (Vsup) 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V
最小供电电压 (Vsup) 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V
标称供电电压 (Vsup) 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
表面贴装 YES YES YES YES YES YES YES YES
技术 CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
温度等级 INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL
端子面层 Tin/Silver/Copper (Sn/Ag/Cu) Tin/Silver/Copper (Sn/Ag/Cu) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Silver/Copper (Sn/Ag/Cu) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Silver/Copper (Sn/Ag/Cu)
端子形式 BALL BALL BALL BALL BALL BALL BALL BALL
端子节距 1.27 mm 1.27 mm 1.27 mm 1.27 mm 1.27 mm 1.27 mm 1.27 mm 1.27 mm
端子位置 BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM
处于峰值回流温度下的最长时间 20 20 NOT SPECIFIED NOT SPECIFIED 20 NOT SPECIFIED NOT SPECIFIED 20
宽度 14 mm 14 mm 14 mm 14 mm 14 mm 14 mm 14 mm 14 mm
厂商名称 Cypress(赛普拉斯) - - Cypress(赛普拉斯) - Cypress(赛普拉斯) Cypress(赛普拉斯) Cypress(赛普拉斯)
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