128K x 36, 256K x 18
Smart ZBT™ 3.3V Synchronous SRAMs
3.3V I/O, Burst Counter
Pipelined Outputs
Features
128K x 36, 256K x 18 memory configurations
Supports high performance system speed - from 66MHz to
133MHz
ZBT
TM
Feature - No dead cycles between write and read
cycles
Smart ZBT
TM
Feature - Eases system timing requirements
and reduces the likelihood of bus contention
With Smart ZBT
TM
the output turn-on (t
CLZ
) is adaptable to
the user's system and is a function of the cycle time
Backward compatible with IDT's existing ZBT offerings
Internally synchronized output buffer enable eliminates the
need to control
OE
Single R/W (READ/WRITE) control pin
W
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
BW
Individual byte write (BW
1
-
BW
4
) control (May tie active)
Three chip enables for simple depth expansion
3.3V power supply (±5%)
3.3V I/O Supply (V
DDQ)
Packaged in a JEDEC standard 100-lead plastic thin quad
flatpack (TQFP) and 119-lead ball grid array (BGA).
Preliminary
IDT71V3566
IDT71V3568
x
x
Description
The IDT71V3566/68 are 3.3V high-speed 4,718,592-bit (4.5 Mega-
bit) synchronous SRAMs. They are designed to eliminate dead bus
cycles when turning the bus around between reads and writes, or
writes and reads. Thus, they have been given the name ZBT
TM
, or
Zero Bus Turnaround.
Address and control signals are applied to the SRAM during one
clock cycle, and two cycles later the associated data cycle occurs, be it
read or write.
The IDT71V3566/68 offer the user a Smart functionality which simplifies
system timing requirements when turning the bus around between writes
and reads. Traditionally, SRAMs are designed with fast turn-on times
(t
CLZ
) in order to meet the requirements of high speed applications. This
fast turn-on may lead to bus contention at slower speeds, i.e. 133 MHz and
slower, since these designs often use less aggressive ASICs/controllers
with loose turn-off parameters (t
CHZ
). Thus at slower speeds, more margin
on the RAM's t
CLZ
may be needed to compensate for the slow turn-off of
the ASIC/controller. The IDT71V3566/68 have the ability to provide this
extra margin by allowing t
CLZ
to adapt to the user's system.
With the Smart ZBT
TM
feature, the output turn-on time (t
CLZ
) adapts to
the user's system and is solely a function of cycle time (t
CYC
). Thus with
Smart ZBT
TM
, t
CLZ
is independent of process, voltage, and temperature
variations. With this deterministic output turn-on feature, the guesswork of
when the SRAM begins to drive the bus is removed, therefore easing
x
x
x
x
x
x
x
x
x
x
x
x
x
Pin Description Summary
A
0
-A
1 7
CE
1
, CE
2
,
CE
2
OE
R/W
CEN
BW
1
,
BW
2
,
BW
3
,
BW
4
CLK
A DV /LD
LBO
I/O
0
-I/O
3 1
, I/O
P 1
-I/O
P 4
V
DD
, V
DDQ
V
SS
A d d re s s Inp uts
Chip E nab le s
Outp ut E nab le
Re ad /W rite S ig nal
Clo c k E nab le
Ind ivid ual B y te W rite S e le cts
Clo ck
A d v anc e b urst ad d re ss / Lo ad ne w ad d re ss
Line ar / Inte rle av e d B urs t Ord e r
Data Inp ut / Outp ut
Co re P o we r, I/O P o we r
Gro und
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
I/O
S up p ly
S up p ly
S ynchro no us
S ynchro no us
A s ync hro no us
S ynchro no us
S ynchro no us
S ynchro no us
N/A
S ynchro no us
S tatic
S ynchro no us
S tatic
S tatic
5295 tbl 01
ZBT and ZeroBus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.
Smart ZBT and Smart Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is also supported by Micron Technology, Inc.
DECEMBER 1999
DSC-5295/00
1
©1999 Integrated Device Technology, Inc.
IDT71V3566, IDT71V3568, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
Smart ZBT™ Feature, 3.3V I/O, Burst Counter, Pipelined Outputs
™
Preliminary
Commercial Temperature Range
Description (cont.)
system timing requirements. The Smart feature allows the turn-on time of
the ZBT
TM
SRAM output drivers (t
CLZ
) to adapt to match the requirements
of the system.
The IDT71V3566/68 contain data I/O, address and control signal
registers. Output enable is the only asynchronous signal and can be used
to disable the outputs at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V3566/68
to be suspended as long as necessary. All synchronous inputs are
ignored when (CEN) is high and the internal device registers will hold
their previous values.
There are three chip enable pins (CE
1
, CE
2
,
CE
2
) that allow the user
to deselect the device when desired. If any one of these three is not asserted
when ADV/LD is low, no new memory operation can be initiated.
However, any pending data transfers (reads or writes) will be completed.
The data bus will tri-state two cycles after the chip is deselected or a write
is initiated.
The IDT71V3566/68 have an on-chip burst counter. In the burst
mode, the IDT71V3566/68 can provide four cycles of data for a single
address presented to the SRAM. The order of the burst sequence is
defined by the
LBO
input pin. The
LBO
pin selects between linear and
interleaved burst sequence. The ADV/LD signal is used to load a new
external address (ADV/LD = LOW) or increment the internal burst counter
(ADV/LD = HIGH).
The IDT71V3566/68 SRAMs utilize IDT's latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-lead thin plastic quad flatpack (TQFP) as well as a 119-lead ball grid
array (BGA).
Pin Definitions
(1)
Sym bol
A
0
-A
1 7
A DV /LD
Pin Function
A d d re ss Inp uts
A d vance / Lo ad
I/O
I
I
Active
N/A
N/A
Description
S ynchro no u s A d d re ss inp uts. The ad d re ss re g iste r is trig g e re d b y a co m b inatio n o f the rising e d g e o f CLK ,
A DV /LD lo w,
CEN
lo w, and true chip e nab le s.
A DV /LD is a sync hro no us inp ut that is use d to lo ad the inte rnal re g iste rs with ne w ad d re ss and co ntro l whe n it is
sam p le d lo w at the rising e d g e o f clo ck with the chip se le c te d . W he n A DV /LD is lo w with the chip d e se le cte d ,
any b urst in p ro g re ss is te rm inate d . W he n A DV /LD is sam p le d hig h the n th e inte rnal b urst co unte r is ad vance d
fo r any b urst that was in p ro g re ss. The e xte rna l ad d re sse s are ig no re d whe n ADV /
LD
is sam p le d hig h.
R/W sig nal is a synchro no us inp ut that id e ntifie s whe the r the curre nt lo ad cycle initiate d is a Re ad o r W rite acce ss
to the m e m o ry array. The d ata b us activity fo r the curre nt cycle take s p lace two clo ck cycle s late r.
S ynchro no us Clo ck E nab le Inp ut. W he n
CEN
is sam p le d hig h, all o the r synchro no us inp uts, includ ing clo ck are
ig no re d and o utp uts re m ain unchang e d . The e ffe ct o f
CEN
sam p le d hig h o n the d e vice o utp uts is as if the lo w
to hig h clo ck transitio n d id no t o ccur. Fo r no rm al o p e ratio n,
CEN
m ust b e sam p le d lo w at rising e d g e o f clo ck.
S ynchro no us b yte write e nab le s. E ach 9-b it b yte has its o wn active lo w b yte write e nab le . On lo ad write cycle s
(W he n R/W and A DV /LD are sam p le d lo w ) the ap p ro p riate b yte write sig nal (BW
1
-BW
4
) m ust b e valid . The b yte
write sig nal m ust also b e valid o n e ach cycle o f a b urst write . B yte W rite sig nals are ig no re d whe n R/
W
is sam p le d
hig h. The ap p ro p riate b yte (s) o f d ata are writte n into the d e vice two cycle s late r.
BW
1
-BW
4
can all b e tie d lo w if
always d o ing write to the e ntire 36-b it wo rd .
S ynchro no us active lo w chip e nab le .
CE
1
and
CE
2
are use d with CE
2
to e nab le the IDT71V 3566/68. (CE
1
o r
CE
2
sam p le d hig h o r CE
2
sa m p le d lo w) and A DV /LD lo w at the rising e d g e o f clo ck, initiate s a d e se le ct cycle . The
ZBT
TM
has a two cycle d e se le ct, i.e ., the d ata b us will tri-state two clo ck cycle s afte r d e se le ct is initiate d .
S ynchro no us active hig h chip e nab le . CE
2
is use d with
CE
1
and
CE
2
to e nab le the chip . CE
2
has inve rte d p o larity
b ut o the rwise id e ntical to
CE
1
and
CE
2
.
This is the clo ck inp ut to the IDT71V 3566/68. E xce p t fo r
OE,
all tim ing re fe re nce s fo r the d e vice are m ad e with
re sp e ct to th e rising e d g e o f CLK.
S ynchro no us d ata inp ut/o utp ut (I/O) p ins. B o th th e d ata inp ut p a th and d ata o u tp ut p ath are re g iste re d and trig g e re d
b y th e rising e d g e o f CLK .
B urst o rd e r se le ctio n inp ut. W he n
LBO
is hig h the Inte rle ave d b urst se q ue nce is se le cte d . W he n
LBO
is lo w the
Line ar b urst se q ue nce is se le cte d .
LBO
is a static inp ut and it m ust no t chang e d uring d e vice o p e ratio n.
A synchro no us o utp ut e nab le .
OE
m ust b e lo w to re ad d ata fro m the 71V 3566/68. W he n
OE
is hig h the I/O p ins
are in a hig h-im p e d ance state .
OE
d o e s no t ne e d to b e active ly co ntro lle d fo r re ad and w rite cycle s. In no rm al
o p e ratio n,
OE
can b e tie d lo w.
3.3V co re p o we r sup p ly.
3.3V I/O S up p ly.
Gro und .
5295 tbl 02
R/W
CEN
Re ad / W rite
Clo ck Enab le
I
I
N/A
LOW
BW
1
-BW
4
Ind ivid ual B yte
W rite Enab le s
I
LOW
CE
1
,
CE
2
Chip Enab le s
I
LOW
CE
2
CLK
I/O
0
-I/O
3 1
I/O
P 1
-I/O
P 4
LBO
OE
Chip Enab le
Clo ck
Data Inp ut/O utp ut
Line ar B urst O rd e r
O utp ut E nab le
I
I
I/O
I
I
HIGH
N/A
N/A
LOW
LOW
V
DD
V
DDQ
V
SS
NOTE:
P o we r S up p ly
P o we r S up p ly
G ro und
N/A
N/A
N/A
N/A
N/A
N/A
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42
2
IDT71V3566, IDT71V3568, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
Smart ZBT™ Feature, 3.3V I/O, Burst Counter, Pipelined Outputs
™
Preliminary
Commercial Temperature Range
Functional Block Diagram
LBO
Address A [0:16]
CE1,
CE2,
CE2
R/W
CEN
ADV/LD
BWx
D
Clk
D
Q
Control
D
Q
128Kx36 BIT
MEMORY ARRAY
Address
Input Register
DI
DO
Q
Control Logic
Mux
Sel
D
Clk
Clock
Output Register
Q
OE
Gate
5295 drw 01a
,
Data I/O [0:31],
I/O P[1:4]
LBO
Address A [0:17]
CE1,
CE2,
CE2
R/W
CEN
ADV/LD
BWx
D
Clk
D
Q
D
Q
256x18 BIT
MEMORY ARRAY
Address
Control
Input Register
DI
DO
Q
Control Logic
Mux
Sel
D
Clk
Clock
Output Register
Q
OE
Gate
5295 drw 01b
,
Data I/O [0:15],
I/O P[1:2]
6.42
3
IDT71V3566, IDT71V3568, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
Smart ZBT™ Feature, 3.3V I/O, Burst Counter, Pipelined Outputs
™
Preliminary
Commercial Temperature Range
Recommended DC Operating
Conditions
Symbol
V
DD
V
DDQ
V
SS
V
IH
V
IH
V
IL
Parameter
Core Supply Voltage
I/O Supply Voltage
Ground
Input High Voltage - Inputs
Input High Voltage - I/O
Input Low Voltage
Min.
3.135
3.135
0
2.0
2.0
-0.3
(1)
Typ.
3.3
3.3
0
____
____
____
Recommended Operating
Temperature and Supply Voltage
Unit
V
V
V
V
V
V
5295 tbl 04
Max.
3.465
3.465
0
V
DD
+0.3
V
DDQ
+0.3
(2)
0.8
Grade
Commercial
Temperature
0°C to +70°C
V
SS
0V
V
DD
3.3V±5%
V
DDQ
3.3V±5%
5295 tbl 05
NOTES:
1. V
IL
(min.) = –1.0V for pulse width less than t
CYC
/2, once per cycle.
2. V
IH
(max.) = +6.0V for pulse width less than t
CYC
/2, once per cycle.
Pin Configuration 128K x 36
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/O
P3
I/O
16
I/O
17
V
DDQ
V
SS
I/O
18
I/O
19
I/O
20
I/O
21
V
SS
V
DDQ
I/O
22
I/O
23
V
SS
(4)
V
DD
V
DD
(1)
V
SS
I/O
24
I/O
25
V
DDQ
V
SS
I/O
26
I/O
27
I/O
28
I/O
29
V
SS
V
DDQ
I/O
30
I/O
31
I/O
P4
CE
2
BW
4
BW
3
BW
2
BW
1
CE
2
V
DD
V
SS
CLK
R/W
CEN
OE
ADV/LD
NC
(2)
NC
(2)
A
8
A
9
A
6
A
7
CE
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O
P2
I/O
15
I/O
14
V
DDQ
V
SS
I/O
13
I/O
12
I/O
11
I/O
10
V
SS
V
DDQ
I/O
9
I/O
8
V
SS
V
DD
(1)
V
DD
V
SS
(4)
I/O
7
I/O
6
V
DDQ
V
SS
I/O
5
I/O
4
I/O
3
I/O
2
V
SS
V
DDQ
I/O
1
I/O
0
I/O
P1
5295 drw 02
,
LBO
A
5
A
4
A
3
A
2
A
1
A
0
DNU
(3)
DNU
(3)
V
SS
V
DD
DNU
(3)
DNU
(3)
Top View
TQFP
NOTES:
1. Pins 16 and 66 do not have to be connected directly to V
DD
as long as the input voltage is
≥
V
IH
.
2. Pins 83 and 84 are reserved for future 8M and 16M respectively.
3. DNU = Do not use
4. Pins 14 and 64 do not have to be connected directly to V
SS
as long as the input voltage is
≤
V
IL
.
6.42
4
A
10
A
11
A
12
A
13
A
14
A
15
A
16
IDT71V3566, IDT71V3568, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
Smart ZBT™ Feature, 3.3V I/O, Burst Counter, Pipelined Outputs
™
Preliminary
Commercial Temperature Range
Pin Configuration 256K x 18
CE
2
NC
NC
BW
2
BW
1
CE
2
V
DD
V
SS
CLK
R/W
CEN
OE
ADV/LD
NC
(2)
NC
(2)
A
8
A
9
A
6
A
7
CE
1
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
V
TERM
(3,6)
V
TERM
(4,6)
V
TERM
(5,6)
T
A
T
BIAS
T
STG
P
T
Rating
Terminal Voltage with
Respect to GND
Terminal Voltage with
Respect to GND
Terminal Voltage with
Respect to GND
Terminal Voltage with
Respect to GND
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
Power Dissipation
DC Output Current
Commercial
-0.5 to +4.6
-0.5 to V
DD
-0.5 to V
DD
+0.5
-0.5 to V
DDQ
+0.5
-0 to +70
-55 to +125
-55 to +125
2.0
50
Unit
V
V
V
V
o
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
NC
NC
V
DDQ
V
SS
NC
NC
I/O
8
I/O
9
V
SS
V
DDQ
I/O
10
I/O
11
V
SS
(4)
V
DD
V
DD
(1)
V
SS
I/O
12
I/O
13
V
DDQ
V
SS
I/O
14
I/O
15
I/O
P2
NC
V
SS
V
DDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
10
NC
NC
V
DDQ
V
SS
NC
I/O
P1
I/O
7
I/O
6
V
SS
V
DDQ
I/O
5
I/O
4
V
SS
V
DD
(1)
V
DD
V
SS
(4)
I/O
3
I/O
2
V
DDQ
V
SS
I/O
1
I/O
0
NC
NC
V
SS
V
DDQ
NC
NC
NC
5295 drw 02a
C
C
C
o
o
W
mA
5295 tbl 06
,
I
OUT
Top View
TQFP
NOTES:
1. Pins 16 and 66 do not have to be connected directly to V
DD
as long as the input
voltage is
≥
V
IH
.
2. Pins 83 and 84 are reserved for future 8M and 16M respectively.
3. DNU = Do not use
4. Pins 14 and 64 do not have to be connected directly to V
SS
as long as the
input voltage is
≤
V
IL
.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
DD
terminals only.
3. V
DDQ
terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed V
DDQ
during power
supply ramp up.
LBO
A
5
A
4
A
3
A
2
A
1
A
0
DNU
(3)
DNU
(3)
V
SS
V
DD
DNU
(3)
DNU
(3)
A
11
A
12
A
13
A
14
A
15
A
16
A
17
(T
A
= +25°C, f = 1.0MHz, TQFP Package)
Symbol
C
IN
C
I/O
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
5
7
Unit
pF
pF
5295 tbl 07
Capacitance
NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
6.42
5
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